Patents by Inventor Michael FATTU

Michael FATTU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10749758
    Abstract: An apparatus for cognitive data center management is disclosed. A computer-implemented method and computer program product also perform the functions of the apparatus. According to an embodiment of the present invention, the apparatus includes a performance module that determines performance metrics over a predetermined time interval at a device coordinate in a three-dimensional (ā€œ3Dā€) coordinate system for each replaceable device of a plurality of replaceable devices within a data center. The apparatus maps the performance metrics to environmental sensor measurements taken in the 3D coordinate system. The apparatus further includes an input analysis module that uses discovery analytics to determine a predicted time to failure for each replaceable device.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khajistha Fattu, Michael Fattu, Prasanna Jayaraman, Tony Sawan, Eakambaram R. Thirumalai
  • Publication number: 20200162342
    Abstract: An apparatus for cognitive data center management is disclosed. A computer-implemented method and computer program product also perform the functions of the apparatus. According to an embodiment of the present invention, the apparatus includes a performance module that determines performance metrics over a predetermined time interval at a device coordinate in a three-dimensional (ā€œ3Dā€) coordinate system for each replaceable device of a plurality of replaceable devices within a data center. The apparatus maps the performance metrics to environmental sensor measurements taken in the 3D coordinate system. The apparatus further includes an input analysis module that uses discovery analytics to determine a predicted time to failure for each replaceable device.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Inventors: KHAJISTHA FATTU, MICHAEL FATTU, PRASANNA JAYARAMAN, TONY SAWAN, EAKAMBARAM R. THIRUMALAI
  • Patent number: 10031050
    Abstract: Embodiments herein describe a universal test platform that includes a universal test station (UTS) coupled to a system under test (SUT) using respective adapters. The adapters include an interface subdivided into portions that are assigned to different data and power standards. In one embodiment, the UTS is coupled to a UTS adapter using a plurality of cables that transmits the different data and power signals between the UTS and the adapter. For example, the interface in the UTS adapter may include a plurality of pins or optical channels that are each coupled to one of the plurality of cables. The SUT is coupled to a SUT adapter which may have the same interface as the UTS adapter. However, the SUT may be coupled to only a sub-portion of the I/O elements in the SUT adapter, and thus, only some of the I/O elements are used when testing the SUT.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Khajistha Fattu, Michael Fattu, Rachael C. Freitas, George Zacharakis-Jutz
  • Publication number: 20180106702
    Abstract: Embodiments herein describe a universal test platform that includes a universal test station (UTS) coupled to a system under test (SUT) using respective adapters. The adapters include an interface subdivided into portions that are assigned to different data and power standards. In one embodiment, the UTS is coupled to a UTS adapter using a plurality of cables that transmits the different data and power signals between the UTS and the adapter. For example, the interface in the UTS adapter may include a plurality of pins or optical channels that are each coupled to one of the plurality of cables. The SUT is coupled to a SUT adapter which may have the same interface as the UTS adapter. However, the SUT may be coupled to only a sub-portion of the I/O elements in the SUT adapter, and thus, only some of the I/O elements are used when testing the SUT.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Inventors: Khajistha FATTU, Michael FATTU, Rachael C. FREITAS, George ZACHARAKIS-JUTZ