Patents by Inventor Michael Fetterman
Michael Fetterman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7103751Abstract: A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.Type: GrantFiled: June 27, 2002Date of Patent: September 5, 2006Assignee: Intel CorporationInventors: Bret L. Toll, John Alan Miller, Michael A. Fetterman
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Patent number: 6393550Abstract: Maximum throughput or “back-to-back” scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.Type: GrantFiled: September 19, 1995Date of Patent: May 21, 2002Assignee: Intel CorporationInventors: Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth
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Patent number: 6101597Abstract: Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM).Type: GrantFiled: December 30, 1993Date of Patent: August 8, 2000Assignee: Intel CorporationInventors: Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth
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Patent number: 6079014Abstract: A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming circuit that allocates execution resources to each instruction, and an execution circuit that executes each instruction in the instruction stream. The execution circuit causes the front end circuit to refetch the series of instructions if a branch misprediction is detected. A stall signal disables the register renaming circuit until the execution circuit commits the branch result to an architectural state according to the program sequence.Type: GrantFiled: September 2, 1997Date of Patent: June 20, 2000Assignee: Intel CorporationInventors: David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Robert P. Colwell, Glenn J. Hinton
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Patent number: 6047369Abstract: A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions.Type: GrantFiled: February 28, 1994Date of Patent: April 4, 2000Assignee: Intel CorporationInventors: Robert P. Colwell, Andrew F. Glew, Atiq A. Bajwa, Glenn J. Hinton, Michael A. Fetterman
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Patent number: 5987600Abstract: A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.Type: GrantFiled: May 5, 1997Date of Patent: November 16, 1999Assignee: INTEL CorporationInventors: David B. Papworth, Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell, Andrew F. Glew
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Patent number: 5974523Abstract: A mechanism for efficiently overlapping multiple operand types is used in a microprocessor which includes a plurality of execution units and a mechanism to provide operations, which include one or more operands, to the plurality of execution units. Each of the plurality of execution units interprets the one or more operands as different types of operands, and the mechanism to provide operations overlaps the different types of operands.Type: GrantFiled: September 6, 1996Date of Patent: October 26, 1999Assignee: Intel CorporationInventors: Andrew F. Glew, Darrell D. Boggs, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell, David B. Papworth
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Patent number: 5951670Abstract: A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for memory segmentation of the processor. A plurality of physical segment registers are coupled to the logical segment registers. The processor further comprises an issue cluster that issues the instructions and that maps the logical segment registers, specified by the operations, to the physical segment registers to provide segment register renaming in the processor.Type: GrantFiled: September 4, 1997Date of Patent: September 14, 1999Assignee: Intel CorporationInventors: Andrew F. Glew, Michael A. Fetterman
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Patent number: 5913050Abstract: This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address.Type: GrantFiled: October 22, 1996Date of Patent: June 15, 1999Assignee: Intel CorporationInventors: Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth
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Patent number: 5889982Abstract: A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is generated therefrom, for example, by referencing a lookup table. The microcode event handler vector is then used for invoking a microcode event handler to handle occurrence of these events in the processor. By the formation of an event vector, and the microcode event handler vector, execution performance is increased due to avoiding conditional branching within the processor, such as modem high performance architectures, including those which execute instructions in and out-of-order.Type: GrantFiled: July 1, 1995Date of Patent: March 30, 1999Assignee: Intel CorporationInventors: Scott Dion Rodgers, Rohit Vidwans, Joel Huang, Michael A. Fetterman, Kamla Huck
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Patent number: 5842036Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.Type: GrantFiled: October 20, 1997Date of Patent: November 24, 1998Assignee: Intel CorporationInventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
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Patent number: 5826094Abstract: A mechanism for indicating within a register alias table (RAT) that certain data has become architecturally visible so that the RAT contains the most recent location of the certain data. Upon receiving the indication that data associated with a particular register is architecturally visible, if a subsequent operation uses the particular register as a source, the data will be supplied from the architecturally visible buffer instead of from an internal buffer (not architecturally visible). The internal buffer is implemented by a reorder buffer (ROB) which contains information associated with instructions that have not yet retired. The architecturally visible buffer is a retirement register file (RRF) which contains information associated with retired instructions.Type: GrantFiled: July 8, 1996Date of Patent: October 20, 1998Assignee: Intel CorporationInventors: Robert P. Colwell, David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton
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Patent number: 5809271Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.Type: GrantFiled: August 23, 1995Date of Patent: September 15, 1998Assignee: Intel CorporationInventors: Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth
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Patent number: 5809325Abstract: An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution.Type: GrantFiled: July 9, 1996Date of Patent: September 15, 1998Assignee: Intel CorporationInventors: Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz
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Patent number: 5778245Abstract: A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance.Type: GrantFiled: March 1, 1994Date of Patent: July 7, 1998Assignee: Intel CorporationInventors: David B. Papworth, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell, Michael A. Fetterman, Shantanu R. Gupta, James S. Griffith
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Patent number: 5751986Abstract: A computer system including a processor having a inherently weakly-ordered memory model comprising a mechanism for emulating strong-ordering to produce self-consistent ordering on a system-wide basis. The processor snoops the system bus externally to determine if a STORE on the external bus hits a LOAD buffer inside the memory subsystem of the processor. If so, the situation is flagged as one which carries the risk of violating processor ordering rules. When the STORE hits the same LOAD address in the LOAD buffer of the processor's memory subsystem, the speculative state of the processor is erased. This cancels the LOAD operation in all subsequent operations. The processor then begins executing from the aborted LOAD; this time loading the newly updated value.Type: GrantFiled: January 3, 1997Date of Patent: May 12, 1998Assignee: Intel CorporationInventors: Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Andrew F. Glew, Robert P. Colwell
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Instruction pointer limits in processor that performs speculative out-of-order instruction execution
Patent number: 5740393Abstract: A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation. The retire circuit also determines whether each speculative instruction pointer exceeds the instruction pointer limit. The retire circuit commits the result data value of each instruction to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.Type: GrantFiled: September 30, 1996Date of Patent: April 14, 1998Assignee: Intel CorporationInventors: Rohit A. Vidwans, Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew -
Patent number: 5729728Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.Type: GrantFiled: September 6, 1996Date of Patent: March 17, 1998Assignee: Intel CorporationInventors: Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth
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Patent number: 5721855Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages.The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results.Type: GrantFiled: July 12, 1996Date of Patent: February 24, 1998Assignee: Intel CorporationInventors: Glenn J. Hinton, David B. Papworth, Andrew F. Glew, Michael A. Fetterman, Robert P. Colwell
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Patent number: 5717882Abstract: A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.Type: GrantFiled: December 11, 1996Date of Patent: February 10, 1998Assignee: Intel CorporationInventors: Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, David B. Papworth, Michael A. Fetterman