Abstract: Systems and methods for synchronization are provided. In some aspects, a method for synchronizing an image sensor is provided. The method includes receiving image data captured using an image sensor that is moving along a pathway, and assembling an image sensor trajectory using the image data. The method also includes receiving position data acquired along the pathway using a position sensor, wherein timestamps for the image data and position data are asynchronous, and assembling a position sensor trajectory using the position data. The method further includes generating a spatial transformation that aligns the image sensor trajectory and position sensor trajectory, and synchronizing the image sensor based on the spatial transformation.

Abstract: Systems and methods for synchronization are provided. In some aspects, a method for synchronizing an image sensor is provided. The method includes receiving image data captured using an image sensor that is moving along a pathway, and assembling an image sensor trajectory using the image data. The method also includes receiving position data acquired along the pathway using a position sensor, wherein timestamps for the image data and position data are asynchronous, and assembling a position sensor trajectory using the position data. The method further includes generating a spatial transformation that aligns the image sensor trajectory and position sensor trajectory, and synchronizing the image sensor based on the spatial transformation.

Abstract: An apparatus and/or method includes localization of a mobile device. The localization technique is calibrated by prompting the mobile device for a collection of static position images for an image-based localization service, sending static position images to the image-based localization service, receiving, for the static position images, a plurality of localization values from the image-based localization service, calculating a correction for the plurality of localization values, and providing a location for the mobile device based on the correction for the plurality of localization values.

Abstract: An apparatus and/or method includes localization of a mobile device. The localization technique is calibrated by prompting the mobile device for a collection of static position images for an image-based localization service, sending static position images to the image-based localization service, receiving, for the static position images, a plurality of localization values from the image-based localization service, calculating a correction for the plurality of localization values, and providing a location for the mobile device based on the correction for the plurality of localization values.

Abstract: Systems and methods are provided to incentivize collection of high definition (HD) map content. The system includes at least one sensor, a communications interface, and a device processor. The sensor is configured to acquire sensor data relating to a feature at a location on a roadway. The communications interface is configured to communicate with at least one other device. The device processor is configured to generate an observation data package from the sensor data, perform, using the location, a spatial query on a blockchain configured to store a plurality of data entries to identify whether any data entries of the plurality of data entries exist for the observation data package. When no data entries exist, the device processor is configured to generate a new data entry for the blockchain for the observation data package, and when a data entry exists, validate the observation data package and augment the existing data entry.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

Abstract: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.

Abstract: By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors.