Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: Space-time transmit diversity spread spectrum receiver architectures and methods are described for reducing interference, particularly the interference observed at a user-end terminal in a W-CDMA 3G mobile communications system. Interpath interference which arises due to non-zero cross and auto correlation of more than one spreading code is suppressed by estimating a transmitted signal stream, or a plurality of such signal streams in the case of a plurality of multipath components, respreading this estimated signal and subtracting non-orthogonal interference contributions from a received signal. The techniques provide an improved bit error rate or equivalently, enhanced capacity for a digital mobile communications network.

Abstract: This invention is generally concerned with reduced power consumption signal processing methods and apparatus, and in particular with techniques for jointly controlling power supply voltage and clock frequency in a receiver to reduce power consumption. A method of reducing the power consumption of a data receiver is described. The receiver is configured to process a received signal using repeated implementations of substantially the same first data processing element, a rate of said repetitions being determined by a clock frequency of said first data processing element.

Abstract: The present invention relates to wireless communication networks particularly for indoor deployment, in which there typically directly exists a rapidly changing multipath propagation environment with limited opportunities for line of sight wireless communication. The present invention provides A wireless communications network for communicating with a mobile terminal; comprising: a number of repeater points each comprising means for communicating with the mobile terminal; an access point comprising means for communicating with the repeater points; the repeater points further comprising means for relaying signals between the terminal and the access point; means for determining a quality measure of signals sent by the terminal and received by the access point via the repeater points; means for selecting one or more repeater points to relay transmission signals from the access point to the terminal, said selection based on said quality measures of the terminal signals received by the access point.

Abstract: A receiver for receiving a CDMA signal comprises a common channel interference cancellation facility operable to cancel common channel interference by applying a common channel interference estimate to the received signal through a weighted hybrid of parallel and serial interference cancellation, and a physical channel self-interference cancellation facility operable to cancel physical channel self-interference by applying an interference estimate to the received signal through a weighted hybrid of parallel and serial interference cancellation.

Abstract: The present invention relates to re-configurable signal processing modules in particular, although not exclusively, for wireless communications terminals. In general terms in one aspect the present invention provides a system for reconfiguring a signal processing module having a number of re-configurable resources such as re-configurable hardware blocks including ASIC's and field programmable logic gate arrays (FPGA's), as well as software modules for implementing different functions and which can be run on a DSP or other processing platform within the signal processing module. The module may be a mobile terminal or a base station in a wireless communications system for example. The system comprises means for generating a commands data structure comprising configuration commands for the resources, and may further comprise means for communicating this data structure to the signal processing module. The module has means for reconfiguring itself using this data structure.