Abstract: Disclosed is a smart cage system for housing and assaying multiple vertebrate animals having at least one inner and outer housing assembly including at least one controller designed to monitor and record data from sensors, the at least one or more sensors operationally synchronized at least one or more of before, in real time, and after sensing an action, wherein data captured by each at least one or more sensors can be synchronized by way of at least one time measuring device. A multi object tracking software system is operationally coupled to at least one optical sensor by the at least one controller, designed to track individuals of the multiple vertebrate animals. At least the outer housing assembly includes at least one or more from a group of ports, slots, shelves, pockets, hooks, fasteners, and sleeves each designed to retain sensors and other elements.

Abstract: Disclosed herein are optimized methods of high efficiency purification of adeno-associated virus (AAV) particles, comprising a step of binding one or more AAV particles with a volume of chromatography resin medium comprising at least one ligand possessing a pan-AAV affinity. The optimized methods are capable of providing purified AAV particles comprising a wide diversity of AAV serotypes without the need to further optimize for a given AAV serotype.

Abstract: The disclosure provides viral vector delivery systems for use in treating diseases or disorders in a subject to whom the viral vector delivery systems are administered, as well as to methods of making and using the viral vector delivery systems.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A broadband/baseband interface device for passing data packets accurately and as swiftly as possible from an interface of one medium, (e.g., Ethernet) through to an interface of another medium (e.g., RF modem) in near real time. Incoming data on the broadband medium is received both at the data RAM where it is stored and in a CRC detection module which performs cyclic redundancy checking calculations upon the packet, sending signals upon calculating positive results to both a CRC counter and to a CRC RAM. When the receipt of a packet from the broadband medium is ended, the signal ends, leaving an unpredictable collection of "dribble" bits. Since each positive CRC calculation was noted by the CRC detector and its indicator was stored in an address in the CRC RAM, the exact end of the packet in the data RAM can be positively identified and distinguished from the random "dribble" bits.