Abstract: An animal tagging system for identifying and assaying multiple vertebrate animals, comprising a plurality of identification tags, each identification tag comprising a body with an identifier display area bearing an identifier, further having a male and a female parts, the identification tags applicable to ear or back skin and readable by human and computer vision from at least 5 cm. At least one controller is designed to monitor and record data from a plurality of sensors. A multi-object tracking software system is operationally coupled to at least one optical sensor, designed to track individual animals by detecting and reidentifying the identification tags, generating trajectories, and aggregating features, using at least one of appearance, motion, interaction, exclusion, and occlusion handling models, synchronized with sensor data via a time-measuring device. At least one physiological software system is designed to analyze sensor and tracking data to measure health parameters.

Abstract: A vertebrate monitoring system and method for a smart cage that has at least one sensor array disposed on the smart cage over monitored vertebrate animals living within the smart cage. At least one sensor is disposed on the at least one sensor array and is designed to, in situ, monitor and collect data from at least one or more of environmental conditions within the smart cage, vertebrate animal physiology, vertebrate animal activity, and vertebrate animal performance levels. At least one video camera assembly is disposed to record top-down views of the smart cage interior and elements therein. At least one light source is designed to illuminate the smart cage interior at intensities and color ranges designed for the at least one camera assembly. At least one audio sensor and audio recorder are designed to collect sounds originating from within the smart cage.

Abstract: Compositions and methods for treating a blood disorder in a subject comprising delivering a nucleic acid molecule including a nucleotide sequence encoding two to six guide RNAs (gRNAs) into a hematopoietic stem cell (HSC), a hematopoietic progenitor cell (HPC), or a population of hematopoietic stem and progenitor cells (HSPCs) are described.

Abstract: A robotic arm assembly and rack assembly that includes at least one computer system and software program designed to operate the robotic arm assembly. An operating assembly includes one or more actuators, controllers, and sensors. A robotic arm assembly is operationally and movably coupled to a rack assembly. A rail assembly is designed to guide the robotic arm assembly along coordinates of a three-dimensional space containing the rack assembly. A center axis stems from a port assembly wherein the tool assembly portion is designed to be directionally vectored within polar coordinates. The robotic arm assembly is designed to engage smart cage assemblies disposed on the rack assemblies from a programmed set of operations.

Abstract: The disclosure provides viral vector delivery systems for use in treating diseases or disorders in a subject to whom the viral vector delivery systems are administered, as well as to methods of making and using the viral vector delivery systems.

Abstract: Disclosed is a smart cage system for housing and assaying multiple vertebrate animals having at least one inner and outer housing assembly including at least one controller designed to monitor and record data from sensors, the at least one or more sensors operationally synchronized at least one or more of before, in real time, and after sensing an action, wherein data captured by each at least one or more sensors can be synchronized by way of at least one time measuring device. A multi object tracking software system is operationally coupled to at least one optical sensor by the at least one controller, designed to track individuals of the multiple vertebrate animals. At least the outer housing assembly includes at least one or more from a group of ports, slots, shelves, pockets, hooks, fasteners, and sleeves each designed to retain sensors and other elements.

Abstract: Disclosed herein are optimized methods of high efficiency purification of adeno-associated virus (AAV) particles, comprising a step of binding one or more AAV particles with a volume of chromatography resin medium comprising at least one ligand possessing a pan-AAV affinity. The optimized methods are capable of providing purified AAV particles comprising a wide diversity of AAV serotypes without the need to further optimize for a given AAV serotype.

Abstract: The disclosure provides viral vector delivery systems for use in treating diseases or disorders in a subject to whom the viral vector delivery systems are administered, as well as to methods of making and using the viral vector delivery systems.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: A router requests a reservation for an egress port prior to dequeuing data from an ingress port data queue. A request is also made for the allocation of a buffer. After the reservation is received and a buffer is allocated, the data is copied the ingress port data queue to the buffer, and an identifier of the buffer is enqueued to an identifier queue of the egress port. After the identifier is dequeued, the data is copied from the buffer to an egress data queue of the egress port, and the buffer is released for reallocation. The buffer can be released prior to completion of the data being copied from the buffer. The queues associated with the egress port determine whether their depths equal or exceed a threshold associated with the respective egress queues. If one or more of the depths does equal or exceed the associated threshold, the granting of reservations for the egress port are postponed.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.