Abstract: At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

Abstract: At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

Abstract: At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.

Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Abstract: A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Abstract: An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.

Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.

Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.

Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.

Abstract: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.

Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.