Abstract: Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Abstract: The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.

Abstract: Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Abstract: The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.