Patents by Inventor Michael Friedemann

Michael Friedemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7745327
    Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 29, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Michael Friedemann, Robert Seidel, Berit Freudenberg
  • Publication number: 20080206986
    Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.
    Type: Application
    Filed: October 12, 2007
    Publication date: August 28, 2008
    Inventors: Axel Preusse, Berit Freudenberg, Michael Friedemann
  • Publication number: 20080182406
    Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.
    Type: Application
    Filed: June 12, 2007
    Publication date: July 31, 2008
    Inventors: Axel Preusse, Michael Friedemann, Robert Seidel, Berit Freudenberg
  • Patent number: 7071096
    Abstract: In forming a thin conductive layer in an interconnect structure by sputter deposition including a re-sputtering step, a flash deposition step is performed after the re-sputtering step to provide a sufficient layer thickness at critical locations, such as at positions of structure irregularities. The flash deposition step may be performed for a fixed process time so that less effort in process control is required while, at the same time, an increased reliability may be obtained compared to conventional approaches without a flash deposition.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Friedemann, Volker Kahlert
  • Patent number: 6984294
    Abstract: A conductive barrier layer may be formed within high aspect ratio openings by a two-step ionizing sputter deposition. The first step is performed at low pressure and low bias power to obtain good coverage of upper portions of the openings. In the second step, the bias power and the pressure are raised to improved directionality of the particles while at the same time increasing the scatter events so that an increased deposition rate at critical structure areas is obtained, thereby achieving a good coverage at lower sidewall areas.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: January 10, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Friedemann, Volker Kahlert
  • Publication number: 20050233582
    Abstract: In forming a thin conductive layer in an interconnect structure by sputter deposition including a re-sputtering step, a flash deposition step is performed after the re-sputtering step to provide a sufficient layer thickness at critical locations, such as at positions of structure irregularities. The flash deposition step may be performed for a fixed process time so that less effort in process control is required while, at the same time, an increased reliability may be obtained compared to conventional approaches without a flash deposition.
    Type: Application
    Filed: January 20, 2005
    Publication date: October 20, 2005
    Inventors: Michael Friedemann, Volker Kahlert
  • Publication number: 20050093155
    Abstract: An improved barrier technology for interconnect features, especially for copper-based interconnects, is provided. A thin titanium nitride liner is conformally deposited by chemical vapor deposition so as to reliably cover all inner surfaces of the interconnect features, even if formed within a porous material, and thus provides a surface area having improved wettability for the deposition of a subsequent barrier material. Hence, the step coverage of a sputter deposition technique, typically used for tantalum-based barrier layers, may be successfully used in combination with the titanium nitride liner, thereby improving the wetting properties for the subsequent copper seed deposition compared to a tantalum-based barrier layer formed by ALD. Moreover, the provision of a CVD titanium nitride liner in combination with a sputter deposited barrier layer assures a significantly higher throughput compared to the conventional atomic layer deposition approach.
    Type: Application
    Filed: June 10, 2004
    Publication date: May 5, 2005
    Inventors: Volker Kahlert, Michael Friedemann
  • Patent number: 6841468
    Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modem IPVD tools.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: January 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Friedemann, Volker Kahlert
  • Publication number: 20040168908
    Abstract: A conductive barrier layer may be formed within high aspect ratio openings by a two-step ionizing sputter deposition. The first step is performed at low pressure and low bias power to obtain good coverage of upper portions of the openings. In the second step, the bias power and the pressure are raised to improved directionality of the particles while at the same time increasing the scatter events so that an increased deposition rate at critical structure areas is obtained, thereby achieving a good coverage at lower sidewall areas.
    Type: Application
    Filed: July 22, 2003
    Publication date: September 2, 2004
    Inventors: Michael Friedemann, Volker Kahlert
  • Publication number: 20040137714
    Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modern IPVD tools.
    Type: Application
    Filed: June 24, 2003
    Publication date: July 15, 2004
    Inventors: Michael Friedemann, Volker Kahlert