Abstract: An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract: An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

Abstract: A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

Abstract: A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Abstract: Disclosed are circuits and methods of identifying defective memory cells among rows and columns of memory cells. In one embodiment, all the memory cells in an array are programmed to conduct with a conventional read voltage applied and not to conduct with a conventional read-inhibit voltage applied. Any rows that conduct with the read-inhibit voltage applied are termed “leaky,” and are defective. Another read-inhibit voltage lower than the conventional level is selected to cause even leaky cells not to conduct. This test read-inhibit voltage is consecutively applied to each row under test. If one of the rows includes a leaky bit, that bit will conduct with the conventional read-inhibit voltage applied but will not conduct with the test read-inhibit voltage applied. The test flow therefore identifies a row as including a leaky bit when a leak is suppressed by application of the test read-inhibit voltage. A redundant row can be provided to replace a row having a leaky bit.

Abstract: A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.

Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

Abstract: A shift register system is disclosed wherein shift registers buffering memory data perform shift operations in response to a set of sub-clock signals. The set of sub-clock signals comprise nested sub-clock signals having non-overlapping transitions formed from a system clock signal or power on reset signal. Each shift register (or bank of shift registers) responds to a different sub-clock signal. As a result, shift operations are spread out over a period of time rather than occurring simultaneously. Thus, the current drawn during each shift operation is similarly spread out over a period of time. The maximum current drawn during any one shift operation is inversely proportional to the number of non-overlapping sub-clock signal. Therefore, the maximum current drawn (i.e., current spike) drawn during memory operations is minimized.

Abstract: A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.

Abstract: A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or −2 V signals to the gate terminals of the PMOS pass transistors, thereby allowing the PMOS pass transistors to selectively pass 0 (zero) Volts during, for example, program operations. A −2 V charge pump is activated to generate the −2 V signal during operations requiring 0 Volt bitline voltages, and is turned off during all other operations.

Abstract: A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.

Abstract: An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

Abstract: The present invention provides for an embedded test circuit in an integrated circuit. The integrated circuit has a plurality of conducting line segments and fuse elements therebetween with each fuse element selectively connectable in series through the crossing line segments and programming circuits between a pair of programming terminals. Each fuse element is also associated with a pair of test lines with each test line connected to one of the line segments having the fuse element between the test lines. Each test line pair is selectively connectable to a pair of test terminals. The resistance of a selected fuse element is measured by selectively passing a current between the first and second programming terminals through the selected fuse element and selectively measuring a voltage drop across the selected fuse element through the pair of test terminals.