Patents by Inventor Michael G. Hack

Michael G. Hack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803720
    Abstract: A highly stable and efficient organic light emitting device with a phosphorescent-doped mixed layer architecture comprises an anode layer; hole injecting layer over the anode layer; a mixed layer over the hole injecting layer, the mixed layer comprising an organic small molecule hole transporting material, an organic small molecule electron transporting material and a phosphorescent dopant; and a cathode layer over the mixed layer. An electron transporting layer may be present between the mixed layer and the cathode layer and a hole transporting layer may be present between the hole injecting layer and the mixed layer.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: October 12, 2004
    Assignee: Universal Display Corporation
    Inventors: Raymond C. Kwong, Michael G. Hack, Theodore Zhou, Julia J. Brown, Tan D. Ngo
  • Patent number: 6683333
    Abstract: A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer. The shared semiconductor layer extends continuously between the first and second transistors, and includes a concentration of dopant that increases a resistivity of the semiconductor layer and reduces a leakage current through the semiconductor layer while permitting functioning of the transistor array.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: January 27, 2004
    Assignee: E Ink Corporation
    Inventors: Peter T. Kazlas, Michael G. Hack, Paul S. Drzaic, Guy M. Danner, Karl R. Amundson
  • Publication number: 20030144034
    Abstract: Interactive, low power, collapsible, intelligent, multi-media display systems for use as hand-held, portable communications devices are disclosed. A display communications device according to the invention can include a housing that contains a processor, radio transceiver means for transmitting and receiving radio signals, and a collapsible display that is mechanically coupled to the housing and electrically coupled to the processor. The display can have a surface area that is larger than any cross-sectional area of the housing. The processor can be adapted to extract display data from input radio signals, and to provide a representation of the display data to the display.
    Type: Application
    Filed: December 6, 2002
    Publication date: July 31, 2003
    Inventors: Michael G. Hack, Scott Seligsohn, Sherwin I. Seligsohn, Richard Hughes Hewitt, Michael Stuart Weaver
  • Publication number: 20020106847
    Abstract: A thin-film transistor array comprises at least first and second transistors. Each of the first and second transistors include a shared silicon layer, i.e., an active layer. The shared semiconductor layer extends continuously between the first and second transistors, and includes a concentration of dopant that increases a resistivity of the semiconductor layer and reduces a leakage current through the semiconductor layer while permitting functioning of the transistor array.
    Type: Application
    Filed: July 12, 2001
    Publication date: August 8, 2002
    Inventors: Peter T. Kazlas, Michael G. Hack, Paul S. Drzaic, Guy M. Danner, Karl R. Amundson
  • Publication number: 20020074935
    Abstract: A highly stable and efficient organic light emitting device with a phosphorescent-doped mixed layer architecture comprises an anode layer; hole injecting layer over the anode layer; a mixed layer over the hole injecting layer, the mixed layer comprising an organic small molecule hole transporting material, an organic small molecule electron transporting material and a phosphorescent dopant; and a cathode layer over the mixed layer. An electron transporting layer may be present between the mixed layer and the cathode layer and a hole transporting layer may be present between the hole injecting layer and the mixed layer.
    Type: Application
    Filed: December 15, 2000
    Publication date: June 20, 2002
    Inventors: Raymond C. Kwong, Michael G. Hack, Theodore Zhou, Julia J. Brown, Tan D. Ngo
  • Patent number: 6107641
    Abstract: An improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser doping technique is applied to fabricate such transistors. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: August 22, 2000
    Assignee: Xerox Corporation
    Inventors: Ping Mei, Rene A. Lujan, James B. Boyce, Christopher L. Chua, Michael G. Hack
  • Patent number: 6020223
    Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: February 1, 2000
    Assignee: Xerox Corporation
    Inventors: Ping Mei, Rene A. Lujan, James B. Boyce, Christopher L. Chua, Michael G. Hack
  • Patent number: 6019796
    Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: February 1, 2000
    Assignee: Xerox Corporation
    Inventors: Ping Mei, Rene A. Lujan, James B. Boyce, Christopher L. Chua, Michael G. Hack
  • Patent number: 5782665
    Abstract: An array is fabricated in which a cell's dark matrix overlaps its cell electrode so that the overlap areas and the dielectric material between them form a storage capacitor. Each cell's dark matrix can overlap the cell's electrode around its perimeter, and the overlap areas of the dark matrix and the electrode can be sufficiently large and the dielectric layer between them can be sufficiently thin that the storage capacitor they form meets the cell's requirements. The dark matrix can be over the cell electrode, with scan lines and data lines in a series of lower layers, or the dark matrix can be below the series of layers that includes scan lines and data lines, with the cell electrode in an opening defined in the series of layers. The dark matrix layer can be electrically connected to a fixed potential.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: July 21, 1998
    Assignee: Xerox Corporation
    Inventors: Richard L. Weisfield, Michael G. Hack, Joel Levine
  • Patent number: 5733804
    Abstract: An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 .mu.m, and can be 0.5 .mu.m.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: March 31, 1998
    Assignee: Xerox Corporation
    Inventors: Michael G. Hack, Rene A. Lujan
  • Patent number: 5717223
    Abstract: An array includes cells, each with a bottom gate amorphous silicon thin film transistor (a-Si TFT). Each a-Si TFT has an undoped amorphous silicon layer over its gate region and extending beyond its edges. Each a-Si TFT also has an insulating region with edges approximately aligned with the edges of its gate region. Two channel leads of doped semiconductor material such as microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer, each overlapping an edge of the insulating region by a distance that is no more than a maximum overlap distance, which in turn is no more than 1.0 .mu.m.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: February 10, 1998
    Assignee: Xerox Corporation
    Inventors: Michael G. Hack, Rene A. Lujan
  • Patent number: 5703382
    Abstract: Cell circuitry in an array on a substrate includes a TFT or other structure with a series of two or more channels and with an intrachannel region between each pair of adjacent channels in the series. Each intrachannel region has a continuously distribution of dopant particles and the distribution of dopant particles in the intrachannel regions together controls reverse gate bias leakage current without significantly reducing ON current. The average dopant density in intrachannel regions can be sufficiently low to ensure that reverse gate bias leakage current is approximately constant across a range of reverse gate bias voltages.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: December 30, 1997
    Assignee: Xerox Corporation
    Inventors: Michael G. Hack, I-Wei Wu
  • Patent number: 5536932
    Abstract: A polysilicon multiplexer for two-dimensional image sensor arrays is provided. Multiplexing the gate and data lines of a two-dimensional image sensor array greatly simplifies the packaging required for large devices with high resolution. The multiplex transistors are polysilicon for required read out speed. The multiplexer structure of polysilicon TFTs and sensor arrays of amorphous silicon TFTs are formed on a single substrate wherein the polysilicon TFTs are formed by laser crystallization on an outer periphery of the substrate.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: July 16, 1996
    Assignee: Xerox Corporation
    Inventors: Michael G. Hack, Richard L. Weisfield, Robert A. Street
  • Patent number: 5401982
    Abstract: In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: March 28, 1995
    Assignee: Xerox Corporation
    Inventors: Tsu-Jae King, Michael G. Hack
  • Patent number: 5366926
    Abstract: A low temperature process for dehydrogenating amorphous silicon using lasers. Dehydrogenation occurs by irradiating one or more areas of a hydrogenated amorphous silicon layer with laser beam pulses at a relatively low energy density. After the multiple laser pulse irradiation at a relatively low energy density, the laser energy density is increased and multiple irradiation at a higher energy density is performed. If after the multiple irradiation at the higher energy density the amorphous silicon hydrogen content is still too high, dehydrogenation proceeds by multiple irradiations at a yet higher energy density. The irradiation at the various energy densities can result in the formation of polysilicon due to melting of the amorphous silicon layer. As irradiation may be selectively applied to the amorphous silicon, an integral amorphous silicon-polysilicon structure may be formed.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: November 22, 1994
    Assignee: Xerox Corporation
    Inventors: Ping Mei, James B. Boyce, Richard I. Johnson, Michael G. Hack, Rene A. Lujan
  • Patent number: 4882295
    Abstract: Double injection field effect transistors, which may be horizontally or vertically arranged, each include a body of semiconductor material extending between two current-carrying electrodes and forming a current path therebetween. The semiconductor body of each may be substantially intrinsic or lightly doped. One or more control electrodes or gates located adjacent to each current path project a variable electric field over the ambipolar path, which modulates current by controlling the amount of charge carriers of both polarities injected into the semiconductor body. In most of the single gate embodiments, the electrodes extend across a portion, preferably a major portion such as 75% or 90%, or the length of the current path, but not the entire length of the current path. The embodiments having a plurality of gates typically have two insulated gates, one extending from the anode electrode and the other extending from the cathode electrode. The gates in a single device may overlap.
    Type: Grant
    Filed: March 27, 1989
    Date of Patent: November 21, 1989
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Wolodymyr Czubatyj, Michael G. Hack, Michael Shur