Abstract: A physical layer (PHY) controller (314) for arbitrating and resetting a bus for devices coupled to a tri-stateable transceiver (316). The controller (314) includes a tri-stateable driver output enable pin (TDOE) and a novel arbitration scheme. A particular priority code and node address are used in the arbitration number used to arbitrate for the bus before resetting the bus.

Abstract: A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions.