Patents by Inventor Michael G. Lee

Michael G. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ANTI-ROR1 MACROCYCLIC PEPTIDES AND COMPOSITIONS
    Publication number: 20240116988
    Abstract: There are disclosed novel anti-ROR1 macrocyclic peptides and their conjugates with general structure of formula (I), which can be used as ROR1 inhibitors.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 11, 2024
    Applicant: BRISTOL-MYERS SQUIBB COMPANY
    Inventors: JENNIFER X. QIAO, VING G. LEE, TAMMY C. WANG, MICHAEL A. POSS
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Method and system for controlling chip warpage during bonding
    Patent number: 8975092
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Chihiro Uchibori, Michael G. Lee
  • Method and system for controlling chip inclination during flip-chip mounting
    Patent number: 8859335
    Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventors: Michael G. Lee, Chihiro Uchibori
  • METHOD AND SYSTEM FOR CONTROLLING CHIP WARPAGE DURING BONDING
    Publication number: 20140145324
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Chihiro Uchibori, Michael G. Lee
  • METHOD AND SYSTEM FOR CONTROLLING CHIP INCLINATION DURING FLIP-CHIP MOUNTING
    Publication number: 20140124917
    Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Michael G. Lee, Chihiro Uchibori
  • Hybrid interconnect technology
    Patent number: 8633592
    Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: January 21, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Michael G. Lee, Chihiro Uchibori
  • Method and system for providing a reliable semiconductor assembly
    Patent number: 8487428
    Abstract: A semiconductor assembly is provided that includes a substrate. A first set of non-conductive hedges is disposed on and protrudes from a first surface of the substrate. A chip is coupled to and spaced apart from the substrate. The chip has a second surface facing the first surface of the substrate. A second set of non-conductive hedges is disposed on and protrudes from the second surface of the chip. The first set of hedges is configured and positioned to engage the second set of hedges to restrict movement of the substrate with respect to the chip. The second set of hedges is configured and positioned to engage the first set of hedges to restrict movement of the chip with respect to the substrate.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventor: Michael G. Lee
  • Hybrid Interconnect Technology
    Publication number: 20130026634
    Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Michael G. Lee, Chihiro Uchibori
  • Method and system for providing a low-profile semiconductor assembly
    Patent number: 8236606
    Abstract: A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: August 7, 2012
    Assignee: Fujitsu Limited
    Inventor: Michael G. Lee
  • SYSTEMS AND METHODS FOR REINFORCING CHIP PACKAGES
    Publication number: 20120032327
    Abstract: In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an array of bonding interconnects configured to provide electrical communication between the chip and a printed circuit board and reinforcement interconnects arranged around an outermost row of the array of bonding interconnects.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Michael G. Lee, Chihiro Uchibori
  • Alignment structures for an optical assembly
    Patent number: 7855377
    Abstract: An optical assembly is provided that includes a substrate. The substrate has one or more optical waveguides. A component is coupled to and spaced apart from the substrate. The component has one or more photodetectors. One or more flexible optical pillars is disposed between the optical waveguides and the photodetectors. The flexible optical pillars are aligned by one or more alignment structures. The flexible optical pillars are optically transmissive and configured to transmit light from the optical waveguides to the photodetectors.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: December 21, 2010
    Assignee: Fujitsu Limited
    Inventor: Michael G. Lee
  • Method and System for Providing a Low-Profile Semiconductor Assembly
    Publication number: 20100267201
    Abstract: A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 21, 2010
    Applicant: Fujitsu Limited
    Inventor: Michael G. Lee
  • Method and system for providing an aligned semiconductor assembly
    Patent number: 7781867
    Abstract: A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Limited
    Inventor: Michael G. Lee
  • Optical beam splitter
    Patent number: 7742666
    Abstract: An optical beam splitter includes an input waveguide, two or more branching arms, two or more fan-out arms, and two or more output waveguides. The input waveguide receives an input light beam. The two or more branching arms are coupled to the input waveguide at a separation point and split the input light beam at the separation point into two or more light beams. Each fan-out arm is coupled to one of the branching arms and fans-out one of the two or more light beams to a predetermined output pitch. Each output waveguide is coupled to one of the fan-out arms and transmits one of the two or more light beams out of the optical beam splitter.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: June 22, 2010
    Assignee: Fujitsu Limited
    Inventors: Michael G. Lee, Alexei L. Glebov, Dashun S. Zhou
  • Dynamic Reconfigurable Optical Interconnect System
    Publication number: 20100054655
    Abstract: An optical interconnect system includes an integrated circuit, at least one optical modulator, and a slab waveguide. The optical modulator is coupled to the integrated circuit and receives an input light beam from a light source and data from a source device and generates a modulated output light beam. The slab waveguide is coupled to the optical modulator and includes at least one input waveguide microlens, a plurality of output waveguide microlenses, and at least one deflector prism. The input waveguide microlens focuses the modulated output light beam from the modulator into a collimated light beam. The deflector prism is coupled to the integrated circuit, receives the collimated light beam from the input waveguide microlens, and deflects the collimated light beam toward one of the output waveguide microlenses according to an input voltage.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Applicant: Fujitsu Limited
    Inventors: Alexei L. Glebov, Michael G. Lee
  • Optical Beam Splitter
    Publication number: 20100046890
    Abstract: An optical beam splitter includes an input waveguide, two or more branching arms, two or more fan-out arms, and two or more output waveguides. The input waveguide receives an input light beam. The two or more branching arms are coupled to the input waveguide at a separation point and split the input light beam at the separation point into two or more light beams. Each fan-out arm is coupled to one of the branching arms and fans-out one of the two or more light beams to a predetermined output pitch. Each output waveguide is coupled to one of the fan-out arms and transmits one of the two or more light beams out of the optical beam splitter.
    Type: Application
    Filed: August 25, 2008
    Publication date: February 25, 2010
    Applicant: Fujitsu Limited
    Inventors: Michael G. Lee, Alexei L. Glebov, Dashun Steve Zhou
  • Optical Modulator
    Publication number: 20100046879
    Abstract: An optical modulator includes an input waveguide, a splitting point, a first interaction arm of length L1, a second interaction arm of length L2 that is unequal in length to the first interaction arm, a recombination point, and an output waveguide. The splitting point receives an incoming continuous wave light beam comprising two or more wavelengths of light from the input waveguide and splits it into a first light beam and a second light beam. The first interaction arm is coupled to the input waveguide and transports the first light beam. The second interaction arm is coupled to the input waveguide and transports the second light beam. The output waveguide is coupled to the first interaction arm and second interaction arm at the recombination point and combines the first light beam and second light beam into an output modulated light beam. The first interaction arm and the second interaction arm comprise an electro-optic material with a refractive index that changes according to a modulation stimulus.
    Type: Application
    Filed: August 25, 2008
    Publication date: February 25, 2010
    Applicant: Fujitsu Limited
    Inventors: Michael G. Lee, Alexei L. Glebov, Dashun Steve Zhou
  • Flexible Optical Pillars for an Optical Assembly
    Publication number: 20100034497
    Abstract: An optical assembly is provided that includes a substrate. The substrate has a set of one or more optical waveguides. A component is coupled to and spaced apart from the substrate by at least one or more mechanical supports. The component has one or more photodetectors. A set of one or more flexible optical pillars is disposed to be positioned between the set of optical waveguides and the photodetectors. The set of flexible optical pillars is optically transmissive and configured to transmit light from the set of optical waveguides to the photodetectors.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 11, 2010
    Applicant: Fujitsu Limited
    Inventors: Alexei L. Glebov, Michael G. Lee
  • Alignment Tolerances for an Optical Assembly
    Publication number: 20100032553
    Abstract: An optical assembly is provided that includes a substrate. The substrate has one or more optical waveguides. A component is coupled to and spaced apart from the substrate. The component has one or more photodetectors. One or more flexible optical pillars is disposed between the optical waveguides and the photodetectors. The flexible optical pillars are aligned by one or more alignment structures. The flexible optical pillars are optically transmissive and configured to transmit light from the optical waveguides to the photodetectors.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 11, 2010
    Applicant: Fujitsu Limited
    Inventor: Michael G. Lee