Patents by Inventor Michael G. Placke

Michael G. Placke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170453
    Abstract: A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.
    Type: Application
    Filed: October 20, 2020
    Publication date: May 23, 2024
    Inventors: Michael G. Placke, Tony Brewer
  • Patent number: 11968797
    Abstract: Memory devices including a substrate supporting at least one semiconductor device thereon. The substrate includes an interface sized, shaped, and configured to provide electrical connection to the at least one semiconductor device, the interface located proximate to an end of the substrate. Engagement structures are located proximate to, and laterally outward from, the interface. The engagement structures extend laterally beyond a remainder of a lateral periphery of the substrate, each engagement structure comprising a first depth at a first portion of the engagement structure and a second, smaller depth at a second, laterally inward portion of the engagement structure. A carrier includes supports shaped, positioned, and configured to be positioned in the second portions of the engagement structures to secure the end of the substrate to the carrier.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Michael G. Placke
  • Publication number: 20220046818
    Abstract: Memory devices may include a substrate supporting at least one semiconductor device thereon. The substrate may include an interface sized, shaped, and configured to provide electrical connection to the at least one semiconductor device, the interface located proximate to an end of the substrate. Engagement structures may be located proximate to, and laterally outward from, the interface. The engagement structures may extend laterally beyond a remainder of a lateral periphery of the substrate, each engagement structure comprising a first depth at a first portion of the engagement structure and a second, smaller depth at a second, laterally inward portion of the engagement structure. A carrier may include supports shaped, positioned, and configured to be positioned in the second portions of the engagement structures to secure the end of the substrate to the carrier.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 10, 2022
    Inventor: Michael G. Placke