Abstract: An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node.

Abstract: A decoupled switched current temperature circuit with compounded .DELTA.V.sub.be includes an amplifier having an inverting input with corresponding non-inverting output and a non-inverting input with a corresponding inverting output; a PN junction connected to the non-inverting input through a first input capacitor and a voltage reference circuit is connected to the inverting input through a second input capacitor; a current supply includes a low current source and a high current source; a switching device applies the high current source to the PN junction and applies the low current source to the PN junction for providing the .DELTA.V.sub.

Abstract: A switched current temperature sensor circuit with compounded .DELTA.V.sub.BE includes an amplifier having an inverting input with a corresponding non-inverting output, and a non-inverting input with a corresponding inverting output; a first PN junction connected to the non-inverting input through a first input capacitor and a second PN junction connected to the inverting input through a second input capacitor; a current supply including a low current source and a high current source; a switching device for applying in the auto zero mode the high current source to a first terminal of the first PN junction and the low current source to a first terminal of the second PN junction for providing the V.sub.BE1 of the first junction to the first capacitor and for providing the V.sub.

Abstract: A switching bandgap reference circuit with compounded .DELTA.V.sub.BE includes an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to the non-inverting input; a second PN junction connected to the inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in the auto zero mode the low current source to a first terminal of the first PN junction and the high current source to a first terminal of the second PN junction for establishing the V.sub.BE, of the first junction at both the inputs of the amplifier and for applying in the valid reference mode the high current source to the first terminal of the first PN junction and the low current source to the first terminal of the second PN junction for establishing the positive .DELTA.V.sub.BE, of the first PN junction to both the inputs of the amplifier and applying the negative .DELTA.V.sub.

Abstract: A digital-to-analog converter comprising a set of identical DAC cells each including: (1) a PNP bipolar current source transistor producing a continuous output current (equal values for all DAC cells), (2) a pair of PMOS switches connected to the collector of the bipolar transistor to divert the output current to either a ground line or a corresponding node of an R/2R ladder, (3) ladder circuitry for maintaining the full-scale ladder voltage below a predetermined level which keeps the PMOS switches in the saturated region of their characteristics, and (4) make-before-break switch control circuitry to close the PMOS switch being activated prior to opening the other PMOS switch.

Abstract: A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for V.sub.ref and A.sub.gnd respectively. The "ON" gate voltage of the A.sub.gnd switch is adjusted in accordance with the value of V.sub.ref, to give switch V.sub.GS equality and therefore "ON" resistance matching with the V.sub.ref switch over a wide range of reference voltage. Circuits are shown for developing the A.sub.gnd gate voltage varying with V.sub.ref.

Abstract: A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of high-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

Abstract: A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of higher-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.