Abstract: The embodiments of the invention provide for the storage of speech phrases. Speech phrases are processed by a speaker-independent speech recognition engine of a voice controlled device. This engine returns a speaker-independent representation of the phrase. The speaker-independent representation is stored. Embodiments of the invention include methods of converting text to speaker-independent representations of speech and speaker-independent representations of speech into text.

Abstract: Voice controlled devices with speech recognition have user assignable appliance names and default appliance names to address and control the voice controlled devices. Methods of controling voice controlled devices include addressing a voice controlled device by name and providing a command.

Abstract: Voice controlled devices with speech recognition have user assignable appliance names and default appliance names to address and control the voice controlled devices. Methods of controling voice controlled devices include addressing a voice controlled device by name and providing a command.

Abstract: The present invention includes a method, apparatus and system for STANDARD VOICE USER INTERFACE AND VOICE CONTROLLED DEVICES as described in the claims. Briefly, a standard voice user interface is provided to control various devices by using standard speech commands. The standard VUI provides a set of standard VUI commands and syntax for the interface between a user and the voice controlled device. The standard VUI commands include an identification phrase to determine if voice controlled devices are available in an environment. Other standard VUI commands provide for determining the names of the voice controlled devices and altering them.

Abstract: A semiconductor memory employs a variety of circuit elements which are used to manipulate the digital information stored within the rows and columns of the memory array. The circuit elements must be manipulated in an ordered sequence with proper relative timing to permit decoding of various addresses and other circuit commands and enabling of various ones of the circuit elements. The plurality of timing signals are generated within the memory by a corresponding plurality of timing generators. Accurate timing and sequencing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator followed by either proper conditioning upon an input signal, such as an address, or by a predetermined delay designed into the timing generator itself.

Abstract: A random access memory system employing dynamic storage wherein each cell comprises a single active element. The memory employs MOS technology and is disposed on a silicon substrate. A plurality of sense amplifiers are disposed in a column substantially bisecting each row of memory cells in the memory array. A single input/output line communicates with all the cells. Two dummy cells are employed on each row line on opposite sides of the sense amplifiers. The value of the signal provided by the dummy cell is approximately mid-way between a "0" signal and a "1" signal provided by the storage cells. A plurality of timing signals are generated within the memory; accurate timing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator.