Abstract: Techniques for reducing waveguide birefringence in an integrated planar lightwave circuit chip incorporating a plurality of different optical devices are described and claimed. Each optical device includes waveguides in which the waveguide cores are each disposed on a respective mesa formation formed in a lower cladding layer. In one method, during fabrication of the waveguides, waveguides cores in different devices on the chip are etched to a different depth in a waveguide lower cladding layer, whereby the height of the mesa formation is different in different devices. The different depths are selected to achieve a desired level of waveguide birefringence, preferably minimum waveguide birefringence, in each device. In another technique dummy waveguides are included in one or more devices on the chip in order to optimize the waveguide birefringence in one or more devices for predetermined mesa height(s) used in the chip, or for different mesa heights in the chip.

Abstract: Techniques for reducing waveguide birefringence in an integrated planar lightwave circuit chip incorporating a plurality of different optical devices are described and claimed. Each optical device includes waveguides in which the waveguide cores are each disposed on a respective mesa formation formed in a lower cladding layer. In one method, during fabrication of the waveguides, waveguides cores in different devices on the chip are etched to a different depth in a waveguide lower cladding layer, whereby the height of the mesa formation is different in different devices. The different depths are selected to achieve a desired level of waveguide birefringence, preferably minimum waveguide birefringence, in each device. In another technique dummy waveguides are included in one or more devices on the chip in order to optimize the waveguide birefringence in one or more devices for predetermined mesa height(s) used in the chip, or for different mesa heights in the chip.