Abstract: A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.