Abstract: An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

Abstract: An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

Abstract: In an embodiment a method for operating an integrated circuit includes sequentially requesting, by a processor of an integrated circuit, different instruction lines; determining, by a first comparator of the integrated circuit, while the processor processes a current instruction line supplied in response to a corresponding request, whether or not at least one of the instructions of the current instruction line is a branch instruction by comparing the at least one of the instructions to reference instructions; executing, by the processor, all instructions of the current instruction line before executing a next instruction line when the at least one instruction is a branch instruction from a program memory of the integrated circuit; and executing, by the processor, all instruction of the current instruction line before executing a next instruction line from first and second volatile memory of the integrated circuit when the at least one instruction is not a branch instruction.

Abstract: A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Abstract: A method for controlling a piezoelectric motor, such that control signals of the motor are periodic non-sinusoidal voltage signals.

Abstract: A method for controlling a piezoelectric motor, such that control signals of the motor are periodic non-sinusoidal voltage signals.

Abstract: A method for operating a watchdog timer associated with a microcontroller that generates refresh commands for the watchdog timer is provided. The refresh commands are separated by a time interval within a predetermined range. The method includes receiving the refresh commands by the watchdog timer, and generating a microcontroller reset command by the watchdog timer when a time interval separating successively received refresh commands is not within the predetermined range. In particular, the generating includes staring a refresh countdown on each receipt of a refresh command by the watchdog timer. A reset countdown is started if the refresh countdown has timed out, and if the refresh countdown has not timed out when a next refresh command is received, then the next refresh command does not restart the reset countdown. The microcontroller reset command is generated if the reset countdown has timed out.

Abstract: A method for operating a watchdog timer associated with a microcontroller that generates refresh commands for the watchdog timer is provided. The refresh commands are separated by a time interval receiving the refresh commands by the watchdog timer, and generating a microcontroller reset command by the watchdog timer when a time interval separating successively received refresh commands is not within the predetermined range. In particular, the generating includes staring a refresh countdown on each receipt of a refresh command by the watchdog timer. A reset countdown is started if the refresh countdown has timed out, and if the refresh countdown has not timed out when a next refresh command is received, then the next refresh command does not restart the reset countdown. The microcontroller reset command is generated if the reset countdown has timed out.