Abstract: An apparatus for selecting one of N requesters of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value specifying which of the N requestors was last selected. A second input receives a second value specifying which of the N requestors is enabled to be selected. A barrel incrementer, coupled to receive the first and second inputs, 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic, coupled to the barrel incrementer, generates a third value specifying which of the N requestors is selected next.

Abstract: A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

Abstract: A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread.

Abstract: An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value specifying which of the N requestors was last selected. A second input receives a second value specifying which of the N requestors is enabled to be selected. A barrel incrementer, coupled to receive the first and second inputs, 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic, coupled to the barrel incrementer, generates a third value specifying which of the N requestors is selected next.

Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.

Abstract: A return data selector is disclosed. A pipelined microprocessor includes N functional units that request to return data to the pipeline. In a given selection cycle, some of the functional units may not be requesting to return data. The return data selector includes a circuit for selecting one of functional units in a round-robin fashion. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the functional units is selected next. The first addend is an N-bit vector where each bit is false if the corresponding functional unit is requesting to return a result to the pipeline. The second addend is a 1-hot vector indicating the last selected functional unit.

Abstract: A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit adds a first addend to a 1-bit left-rotated version of a second addend to generate a sum and a carry-out bit. The circuit includes the carry-out bit as a carry-in bit of the add to generate the sum. The sum is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread.

Abstract: The present invention provides one or more synthesized assertions in a self-correcting processor, and applications thereof. In an embodiment, a synthesized assertion detects a mismatch between actual processor behavior and specified or expected processor behavior. When unexpected processor behavior is encountered, the synthesized assertion alters operation of the processor and causes the processor to behave in the specified or expected manner. Synthesized assertions in accordance with the present invention can detect and correct, for example, exception processing errors, instruction address errors, instruction opcode errors, and errors that can cause a processor to stall, as well as various other types of errors.

Abstract: An apparatus for selecting one of N transaction queues from which to transmit a transaction out a switch port. P round-robin vectors of P queue priorities each have N bits that are a 1-bit left-rotated and subsequently sign-extended version of an N-bit input vector with a single bit true corresponding to the last queue selected at the priority. N P-input muxes each receive a corresponding bit of each round-robin vector and select one of the inputs specified by its queue priority. Selection logic receives a transaction from each queue and selects one transaction corresponding the queue having a transmit value greater than or equal to the queues left thereof in the input vectors. Each queue's transmit value comprises a least-significant bit equal to the corresponding mux output, a most-significant bit that is true if its transaction is transmittable, and middle bits comprising the queue priority. Each queue priority is dynamically updatable.

Abstract: An apparatus selects one of N transaction queues from which to transmit a transaction out a port of a switch. A first input value specifies the last-selected queue. Only one of the N bits of the first value corresponding to the last selected queue is true. A second input value specifies which queue is enabled for selection. Each of the N bits of the second value whose corresponding queue is enabled is false. A barrel incrementer 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic generates a third value specifying which queue is selected next. The third value is a Boolean AND of the sum and an inverted version of the second value. Only one of the N bits of the third value corresponding to the next selected one of the queues is true.

Abstract: A bifurcated selector for transmitting transactions from a plurality of transaction queues out a port of a switch. A transaction scheduler selects transactions of the queues for transmission to a device coupled to the port. A policy manager enforces a scheduling policy of the queues. An interface couples the policy manager to the transaction scheduler. The interface includes first signals for the transaction scheduler to receive from the policy manager a priority for each queue. The transaction scheduler selects the transactions for transmission to the device based on the priorities. The interface also includes second signals for the policy manager to receive from the transaction scheduler transaction transmission information for each queue. The policy manager updates the priorities based on the transaction transmission information. The transaction transmission information comprises an indication of which of the queues a transaction was selected from for transmission.

Abstract: An apparatus for selecting one of a plurality of transaction queues from which to transmit a transaction out of a port of a switch. The apparatus includes a group indicator, for each of the queues, for indicating which one of a plurality of groups of the queues the queue belongs to. The apparatus also includes a group priority indicator, for each group of the plurality of groups, for indicating a priority of the group, the priority indicating a priority for transmitting transactions of the queues of the group relative to other groups of the plurality of groups. The apparatus includes selection logic, coupled to the group indicators and the priority indicators, configured to select a queue of the queues, for transmitting out of the port a transaction thereof, based on the group indicators and the group priority indicators.

Abstract: The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in architectural state from occurring as a result of execution of a specific sequence of instruction types. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor.

Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.