Abstract: A multiple scalable radar on chip (SROC) based system in a multi-array configuration; may include: a first SROC; and a second SROC. The first SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The second SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The ramp generator of the first SROC may be configured to drive the fractional-N PLL synthesizer of the second SROC. The fractional-N PLL synthesizer of the second SROC may be configured to produce radio frequency (RF) ramp signals to drive both the first and second SROCs. ‘Y’ and ‘Z’ may represent positive integers.

Abstract: A multiple radar on chip based system is disclosed in the present invention which mainly comprises a ramp generator which is configured to input and process a digital signal and convert it into a digital ramp signal. The fractional-N PLL synthesizer receives the digital ramp signal from the ramp generator and compares it with reference input signal to provide analog RF ramp signal. A frequency multiplier is provided to receive the analog RF ramp signal from the fractional N-PLL synthesizer and generates a local oscillator output signal which is sent to a plurality of receiver chains as output signal. These receiver chains receive amplified analog signal input from the power amplifier also as an output and then after comparing the frequency of local oscillator output and amplified analog signal input, final output is processed. The ramp generator and fractional-N PLL synthesizer may be off chip.

Abstract: A digital filter processor employs four multiplier-accumulator cells and an output accumulator for receiving and accumulating all cell outputs. Data is provided to all cells in parallel, and finite impulse coefficients are applied serially to all cells. A plurality of registers and at least one multiplexer interconnect the cells for transmitting the coefficients between cells. The registers can be employed for sample rate reduction or decimation. A plurality of processors can be cascaded for processing an increased number of coefficients without a reduction in sample time. Alternatively, data can be recycled in a processor to accommodate a number of coefficients greater than the number of cells at a reduced sampled sample rate. A cell address is provided for selecting cell outputs during the reading of the filtered/processed data.