Patents by Inventor Michael Gribelyuk
Michael Gribelyuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11763973Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.Type: GrantFiled: August 13, 2021Date of Patent: September 19, 2023Assignee: Western Digital Technologies, Inc.Inventors: Quang Le, Brian R. York, Cherngye Hwang, Susumu Okamura, Michael Gribelyuk, Xiaoyong Liu, Kuok San Ho, Hisashi Takano
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Publication number: 20230047223Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Susumu OKAMURA, Michael GRIBELYUK, Xiaoyong LIU, Kuok San HO, Hisashi TAKANO
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Patent number: 11495741Abstract: A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation.Type: GrantFiled: June 30, 2020Date of Patent: November 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Brian R. York, Cherngye Hwang, Alan Spool, Michael Gribelyuk, Quang Le
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Publication number: 20210408370Abstract: A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Brian R. YORK, Cherngye HWANG, Alan SPOOL, Michael GRIBELYUK, Quang LE
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Publication number: 20070262348Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.Type: ApplicationFiled: July 24, 2007Publication date: November 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dae-Gyu Park, Oleg Gluschenkov, Michael Gribelyuk, Kwong Wong
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Publication number: 20070152276Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Arnold, Glenn Biery, Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Michael Gribelyuk, Young-Hee Kim, Barry Linder, Vijay Narayanan, Joseph Newbury, Vamsi Paruchuri, Michelle Steen
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Publication number: 20070138578Abstract: A compound metal comprising MOxNy which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MOxNy compound metal. Furthermore, the MOxNy metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (PMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.Type: ApplicationFiled: December 19, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Alessandro Callegari, Michael Gribelyuk, Vijay Narayanan, Vamsi Paruchuri, Sufi Zafar
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Publication number: 20060289903Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: August 30, 2006Publication date: December 28, 2006Inventors: Wanda Andreoni, Alessandro Callegari, Eduard Cartier, Alessandro Curioni, Christopher D'Emic, Evgeni Gousev, Michael Gribelyuk, Paul Jamison, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Carlo Pignedoli, Joseph Shepard, Sufi Zafar
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Publication number: 20060163630Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.Type: ApplicationFiled: January 13, 2005Publication date: July 27, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alessandro Callegari, Michael Gribelyuk, Dianne Lacey, Fenton McFeely, Katherine Saenger, Sufi Zafar
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Publication number: 20060138603Abstract: A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.Type: ApplicationFiled: November 17, 2005Publication date: June 29, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Alessandro Callegari, Michael Gribelyuk, Paul Jamison, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Deborah Neumayer, Pushkar Ranade, Sufi Zafar
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Publication number: 20060057797Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.Type: ApplicationFiled: November 4, 2005Publication date: March 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Andres Bryant, Percy Gilbert, Michael Gribelyuk, Edward Maciejewski, Renee Mo, Shreesh Narasimha
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Publication number: 20060024934Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Huajie Chen, Michael Gribelyuk, Judson Holt, Woo-Hyeong Lee, Ryan Mitchell, Renee Mo, Dan Mocuta, Werner Rausch, Paul Ronsheim, Henry Utomo
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Publication number: 20050280105Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: June 22, 2004Publication date: December 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanda Andreoni, Alessandro Callegari, Eduard Cartier, Alessandro Curioni, Christopher D'Emic, Evengi Gousev, Michael Gribelyuk, Paul Jamison, Rajarao Jammy, Dianne Lacey, Fenton McFeely, Vijay Narayanan, Carlo Pignedoli, Joseph Shepard, Sufi Zafar
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Publication number: 20050282341Abstract: The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 ?; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 ?.Type: ApplicationFiled: June 16, 2004Publication date: December 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dae-Gyu Park, Oleg Gluschenkov, Michael Gribelyuk, Kwong Wong
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Publication number: 20050158924Abstract: A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.Type: ApplicationFiled: January 20, 2004Publication date: July 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima Chakravarti, Bruce Doris, Romany Ghali, Oleg Gluschenkov, Michael Gribelyuk, Woo-Hyeong Lee, Anita Madan
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Publication number: 20050064635Abstract: A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains.Type: ApplicationFiled: September 22, 2003Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Atul Ajmera, Andres Bryant, Percy Gilbert, Michael Gribelyuk, Edward Maciejewski, Renee Mo, Shreesh Narasimha