Abstract: A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p?-doped epitaxial first layer disposed on the drift zone, a heavily n-doped second layer disposed on the first layer, and a terminal formed by p+ implantation, the first layer being in electrical contact with the terminal and being disposed laterally between the terminal and a trench, the trench being formed in the drift zone, in the first layer, and in the second layer. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.

Abstract: A transistor, including a substrate of a first doping type; an epitaxy layer of the first doping type above the substrate; a channel layer of a second doping type, differing from the first doping type, above the epitaxy layer; a plurality of trenches in the channel layer, which have a gate electrode situated below the trenches and are bordered by a source terminal of the first doping type above the channel layer; a plurality of shielding areas of the second doping type, which are situated below the gate electrode. The shielding areas are guided below the trenches together in a interconnection of shielding areas, and several shielding areas are jointly guided to terminals for contacting the shielding areas.

Abstract: A transistor, including a substrate of a first doping type; an epitaxy layer of the first doping type above the substrate; a channel layer of a second doping type, differing from the first doping type, above the epitaxy layer; a plurality of trenches in the channel layer, which have a gate electrode situated below the trenches and are bordered by a source terminal of the first doping type above the channel layer; a plurality of shielding areas of the second doping type, which are situated below the gate electrode. The shielding areas are guided below the trenches together in a interconnection of shielding areas, and several shielding areas are jointly guided to terminals for contacting the shielding areas.

Abstract: A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an AlGaN/GaN heterostructure, having the steps of: generation of a gate electrode by patterning a semiconductor layer that is applied onto the heterostructure, the semiconductor layer encompassing, in particular, polysilicon; application of a passivating layer onto the semiconductor layer; formation of drain regions and source regions by generation of first vertical openings that extend at least into the heterostructure; generation of ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal at least to the height of the passivating layer; and application of a second metal layer onto the ohmic contacts, the second metal layer projecting beyond the passivating layer.

Abstract: A cam phaser (30, 130, 230) dynamically adjusts a rotational relationship of a camshaft (32) of an internal combustion engine with respect to an engine crankshaft operably connected with a phaser sprocket (42, 142, 242). The cam phaser (30, 130, 230) can include a planetary gear assembly having a ring gear (34, 134, 234) driven by the phaser sprocket (42, 142, 242), a planetary gear carrier (36, 136, 236) connected to the camshaft (32), a sun gear (38, 138, 238), and at least one rotatable planetary gear (40, 140, 240).

Abstract: A method for manufacturing a transistor having high electron mobility, encompassing a substrate having a heterostructure, in particular an AlGaN/GaN heterostructure, having the steps of: generation of a gate electrode by patterning a semiconductor layer that is applied onto the heterostructure, the semiconductor layer encompassing, in particular, polysilicon; application of a passivating layer onto the semiconductor layer; formation of drain regions and source regions by generation of first vertical openings that extend at least into the heterostructure; generation of ohmic contacts in the drain regions and in the source regions by partly filling the first vertical openings with a first metal at least to the height of the passivating layer; and application of a second metal layer onto the ohmic contacts, the second metal layer projecting beyond the passivating layer.

Abstract: An SiC trench transistor having a first terminal and an epitaxial layer positioned vertically between a gate trench and a second terminal; a compensation layer extending horizontally being provided in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer. A method for manufacturing an SiC trench transistor is also provided, an epitaxial layer being provided on a second terminal of the SiC trench transistor; a compensation layer extending horizontally being implanted in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer; and a first terminal and a gate trench being provided above the compensation layer.

Abstract: A cam phaser (30, 130, 230) dynamically adjusts a rotational relationship of a camshaft (32) of an internal combustion engine with respect to an engine crankshaft operably connected with a phaser sprocket (42, 142, 242). The cam phaser (30, 130, 230) can include a planetary gear assembly having a ring gear (34, 134, 234) driven by the phaser sprocket (42, 142, 242), a planetary gear carrier (36, 136, 236) connected to the camshaft (32), a sun gear (38, 138, 238), and at least one rotatable planetary gear (40, 140, 240).

Abstract: An SiC trench transistor having a first terminal and an epitaxial layer positioned vertically between a gate trench and a second terminal; a compensation layer extending horizontally being provided in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer. A method for manufacturing an SiC trench transistor is also provided, an epitaxial layer being provided on a second terminal of the SiC trench transistor; a compensation layer extending horizontally being implanted in the epitaxial layer, the compensation layer having an effective doping of a type opposite to the doping of the epitaxial layer; and a first terminal and a gate trench being provided above the compensation layer.

Abstract: A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p?-doped epitaxial first layer disposed on the drift zone, a heavily n-doped second layer disposed on the first layer, and a terminal formed by p+ implantation, the first layer being in electrical contact with the terminal and being disposed laterally between the terminal and a trench, the trench being formed in the drift zone, in the first layer, and in the second layer. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.

Abstract: A method for forming a contact on a semiconductor substrate includes: applying a metal to an exposed partial area of an outer side of the semiconductor substrate and/or of a layer applied to the semiconductor substrate, the partial area being surrounded by at least one edge region of an insulating layer, and the at least one edge region of the insulating layer being at least partially covered by the metal; heating the semiconductor substrate, whereby the metal which is applied to the exposed partial area reacts with at least one semiconductor material of the partial area to form a semiconductor-metal material as the end material or a further processing material of the at least one contact; and etching using an etching material having a higher etching rate for the metal than for the semiconductor-metal material.