Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

Abstract: An adjustable musical instrument neck stiffener includes a beam fabricated by embedding uni-directional material only at the upper portion of the beam, and constrained by braid or bias weave material. In a preferred embodiment, the uni-directional layers are preferably made from carbon fiber tow, cloth, or pultruded carbon fiber and the braid or bias weave material is made of carbon fibers. To reduce weight, the middle section of the beam is preferably hollow. A threaded rod and threaded sleeve provide a way to adjust the neck stiffener beam curvature so that it is straight while under string tension.

Abstract: An adjustable musical instrument neck stiffener includes a beam fabricated by embedding uni-directional material only at the upper portion of the beam, and constrained by braid or bias weave material. In a preferred embodiment, the uni-directional layers are preferably made from carbon fiber tow, cloth, or pultruded carbon fiber and the braid or bias weave material is made of carbon fibers. To reduce weight, the middle section of the beam is preferably hollow. A threaded rod and threaded sleeve provide a way to adjust the neck stiffener beam curvature so that it is straight while under string tension.

Abstract: The present invention provides isolated nucleic acids encoding insect G protein-coupled receptor (GPCR) polypeptides, isolated insect GPCR polypeptides, and uses thereof. Further provided are recombinant proteins and methods for identifying inhibitors to these proteins. The disclosed insect GPCR nucleic acids and polypeptides can be used in screening assays to identify modulating compounds. Protein inhibitors active in the methods disclosed herein are useful as insecticidal, ectoparasiticidal, antiparasitic, anthenenthic and acaracidal agents.

Abstract: An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted.

Abstract: An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation.

Abstract: An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command signals and at least one multiplexer unit which directly controls transfers between the memory module and any one of a plurality of peripheral devices coupled to different ports of the multiplexer unit. The system interface unit operatively provides connections between different ones of the modules during the execution of commands included within user programs. The multiplexer unit includes sets of registers selectable under program control which store information which enables user programs for accessing the memory module.