Abstract: An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.

Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.

Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.

Abstract: A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS, and a memory device located in electrical series with the OTS selector.

Abstract: A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.

Abstract: A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.

Abstract: A MRAM memory cell comprises a SHE layer, a magnetic bit layer with perpendicular anisotropy and an Oersted layer. The magnetic bit layer has a switchable direction of magnetization in order to store data. Data is written to the MRAM memory cell using the Spin Hall Effect so that spin current generated in the SHE layer exerts a torque on the magnetic bit layer while the Oersted layer provides heat and an Oersted field to enable deterministic switching. Data is read form the MRAM memory cell using the Anomalous Hall Effect and sensing voltage at the Oersted layer.

Abstract: A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.

Abstract: A MRAM memory cell comprises a SHE layer, a magnetic bit layer with perpendicular anisotropy and an Oersted layer. The magnetic bit layer has a switchable direction of magnetization in order to store data. Data is written to the MRAM memory cell using the Spin Hall Effect so that spin current generated in the SHE layer exerts a torque on the magnetic bit layer while the Oersted layer provides heat and an Oersted field to enable deterministic switching. Data is read form the MRAM memory cell using the Anomalous Hall Effect and sensing voltage at the Oersted layer.

Abstract: A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.

Abstract: A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

Abstract: A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

Abstract: A surge protection device contains a first electrode, a second electrode electrically connected to electrical ground, and a field-induced switching component electrically contacting the first electrode and the second electrode. The field-induced switching component can include a correlated-electron material or a volatile conductive bridge.

Abstract: The present disclosure relates to a magnetic medium that includes a substrate and a bit patterned magnetic layer applied to the substrate. The bit-patterned magnetic layer includes islands and each island includes a first magnetic material having a first magnetic anisotropy and that has a top surface, a bottom surface, and a peripheral surface. Each island also includes a second magnetic material covering the peripheral surface of the first magnetic material and having a second magnetic anisotropy that is higher than the first magnetic anisotropy. In one embodiment, the first magnetic material may comprise a nucleation domain in a centrally located surface portion of the magnetic islands and/or the second magnetic material may comprise an outer shell on the peripheral surface of the islands.

Abstract: The present disclosure relates to a magnetic medium that includes a substrate and a bit patterned magnetic layer applied to the substrate. The bit-patterned magnetic layer includes islands and each island includes a first magnetic material having a first magnetic anisotropy and that has a top surface, a bottom surface, and a peripheral surface. Each island also includes a second magnetic material covering the peripheral surface of the first magnetic material and having a second magnetic anisotropy that is higher than the first magnetic anisotropy. In one embodiment, the first magnetic material may comprise a nucleation domain in a centrally located surface portion of the magnetic islands and/or the second magnetic material may comprise an outer shell on the peripheral surface of the islands.