Patents by Inventor Michael Grubman
Michael Grubman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11573290Abstract: Illustrative methods and circuits to verify operation of phase shifters. One illustrative method includes: obtaining a first set of in-phase and quadrature components (I1,Q1) of a phase shifter output signal with a first setting; measuring a second set of components (I2,Q2) with a second setting, the second setting being offset from the first by a predetermined phase difference; and combining the first and second sets to determine whether their relationship corresponds to the predetermined phase difference. An illustrative transmitter includes: a phase shifter, an I/Q mixer, and a processing circuit. The phase shifter converts a transmit signal into an output signal having a programmable phase shift. The I/Q mixer mixes the output signal with a reference signal to obtain in-phase and quadrature components of the output signal. The processing circuit is coupled to the I/Q mixer implement the disclosed method.Type: GrantFiled: September 3, 2020Date of Patent: February 7, 2023Assignee: AyDee Kay LLCInventors: Tom Heller, Michael Grubman, Yaniv Maroz, Oded Katz
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Publication number: 20220003839Abstract: Illustrative methods and circuits to verify operation of phase shifters. One illustrative method includes: obtaining a first set of in-phase and quadrature components (I1,Q1) of a phase shifter output signal with a first setting; measuring a second set of components (I2,Q2) with a second setting, the second setting being offset from the first by a predetermined phase difference; and combining the first and second sets to determine whether their relationship corresponds to the predetermined phase difference. An illustrative transmitter includes: a phase shifter, an I/Q mixer, and a processing circuit. The phase shifter converts a transmit signal into an output signal having a programmable phase shift. The I/Q mixer mixes the output signal with a reference signal to obtain in-phase and quadrature components of the output signal. The processing circuit is coupled to the I/Q mixer implement the disclosed method.Type: ApplicationFiled: September 3, 2020Publication date: January 6, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tom HELLER, Michael GRUBMAN, Yaniv MAROZ, Oded KATZ
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Patent number: 10911094Abstract: An array of one or more integrated circuits includes at least one local input port to receive a chirp signal from a local generator; one or more primary input ports to each receive a respective chirp signal from a remote source; a primary switch arrangement operable to switch between the chirp signals from the at least one local input port and the one or more primary input ports to produce a composite signal having a chirp sequence with at least one chirp that begins during a settling period of a previous chirp; and one or more primary output ports to supply a local oscillator signal to a transmitter and a receiver based on the composite signal. The roles of master circuit and follower circuit can change during operation of the array.Type: GrantFiled: November 26, 2019Date of Patent: February 2, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tom Heller, Danny Elad, Oded Katz, Michael Grubman, Benny Sheinman, Dan Corcos
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Patent number: 10698812Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: GrantFiled: August 26, 2019Date of Patent: June 30, 2020Assignee: International Business Machines CorporationInventors: Michael Bar-Joshua, Bartholomew Blaner, Yiftach Benjamini, Michael Grubman
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Patent number: 10572381Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: GrantFiled: December 14, 2017Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
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Patent number: 10565102Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: GrantFiled: July 19, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
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Patent number: 10552313Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: GrantFiled: February 6, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
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Publication number: 20190377673Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: ApplicationFiled: August 26, 2019Publication date: December 12, 2019Inventors: Michael Bar-Joshua, Bartholomew Blaner, Yiftach Benjamini, Michael Grubman
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Publication number: 20190026219Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: ApplicationFiled: December 14, 2017Publication date: January 24, 2019Inventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
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Publication number: 20190026218Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman
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Publication number: 20190026221Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.Type: ApplicationFiled: February 6, 2018Publication date: January 24, 2019Inventors: Michael Bar-Joshua, Yiftach Benjamini, Bartholomew Blaner, Michael Grubman