Abstract: The task of the present invention is to realize chips of different sizes, in particular FPGAs, without the need for ever new production mask sets. In the conventional way, a single die can be used or almost any number of dies from one wafer. According to the invention, only one lithography mask set is used for chip production and multi-die chips of different sizes with 1 . . . n single dies are separated from a wafer. The single dies are connected by the scribeline between the dies. According to the patent claims, various precautions must be taken to ensure that the dies are reliably connected and that no problems occur when separating the multi-die chips.

Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. It is especially important to use an efficient structure, i.e. a structure whose chip area is as small as possible and which is able to realize short and fast signal paths. The task of the present invention is to significantly reduce the effort for the interconnection structures while still maintaining good routeability. This is achieved by the fact that there is no longer a switchbox (SB) on each coordinate position. It is particularly advantageous to arrange the SBs in a chessboard-like manner and also to use two SBs of different sizes which are arranged in a superordinate chessboard structure.

Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. The present invention is based on the task to present a switchbox with a small number of multiplexers and configuration bits, which can both forward a signal in signal direction and can implement a change of direction. The task is solved by using switchboxes consisting of direction multiplexers and at least one direction change multiplexer. Thus the signal direction can be changed arbitrarily without increasing the size of the direction change multiplexers.

Abstract: The task of the present invention is to realize chips of different sizes, in particular FPGAs, without the need for ever new production mask sets. In the conventional way, a single die can be used or almost any number of dies from one wafer. According to the invention, only one lithography mask set is used for chip production and multi-die chips of different sizes with 1 . . . n single dies are separated from a wafer. The single dies are connected by the scribeline between the dies. According to the patent claims, various precautions must be taken to ensure that the dies are reliably connected and that no problems occur when separating the multi-die chips.

Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. The present invention is based on the task to present a switchbox with a small number of multiplexers and configuration bits, which can both forward a signal in signal direction and can implement a change of direction. The task is solved by using switchboxes consisting of direction multiplexers and at least one direction change multiplexer. Thus the signal direction can be changed arbitrarily without increasing the size of the direction change multiplexers.

Abstract: Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. It is especially important to use an efficient structure, i.e. a structure whose chip area is as small as possible and which is able to realize short and fast signal paths. The task of the present invention is to significantly reduce the effort for the interconnection structures while still maintaining good routeability. This is achieved by the fact that there is no longer a switchbox (SB) on each coordinate position. It is particularly advantageous to arrange the SBs in a chessboard-like manner and also to use two SBs of different sizes which are arranged in a superordinate chessboard structure.

Abstract: The present invention relates, generally, to an encryption and decryption system, and, more particularly, to an encryption system utilizing a one-time pad key. The task of the invention is to create a practically feasible 100% secure encryption process that is convenient to use. A random numbers generator or random bit generator of outstanding quality is used. Such ideal chances will then be recorded on a data storage device for later encryption purposes. It is important in the context that said storage device would be kept in a safe place or, in the case of encrypted data transmission, would be physically delivered to the recipient via a trustworthy transmission route. Since a secure encryption is only assured if the key or keys is/are used only a single time, it will be expedient, for information to be recorded on the basis of the keys used. Only in this case the one-time pad key can be found again for decryption. For decryption the formerly recorded key is used.

Abstract: Some Gate Arrays and in particular Filed Programmable Gate Arrays (FPGAs), realize combinatorial logic by utilizing so-called “Look Up Tables” (LUTs). Unfortunaltely the circuit expenditure for a LUT is exponentially increasing with the number of inputs. The invention overcomes this problem by using a set of gates as AND, NAND, OR, NOR, XOR, XNOR, AND/OR combination gate, AND/NOR combination gate, OR/AND combination gate, OR/NAND combination gate, identity comparator between two vectors, multiplexer and adder. In addition, conventional GAs and FPGAs utilize routing structures and channels that allow a so-called Manhattan routing. This has the disadvantage that the signal delay on such a connection is highly dependent on the number of serially linked sections. Consequently, the delay time fluctuates significantly on different connections. The invention overcomes this problem by using a X/Y routing structure with a fixed number of connection points and a fixed local routing.

Abstract: The present invention shows a high speed ADC which can be implemented easily and with low cost into a pure digital integrated circuit. This is realized by converting the analog input voltage into a pulse signal and measuring the pulse signal in length with the help of a delay line and an edge detector. With an XOR gate the input pulse can be converted into two pulses of different lengths. With a special calculation circuitry the digital output value becomes independent of the reference frequency used.

Abstract: Liquid margarines and other pourable dispersions which contain a hardstock fat derived from plant waxes. The fat consists of a mixture of triglycerides, which fat is non-hydrogenated and contains less than 10 wt. % of fatty acid residues with a chain length of 6–10 carbon atoms, of which less than 50 wt. % of the triglycerides consist of monoacyl triglycerides and which fat is characterized in that its content of fatty acid residues which are saturated and contain at least 20 carbon atoms is at least 30 wt. %, preferably at least 40 wt. % and more preferably at least 50 wt. % calculated on total fatty acid residues. Such fat can be obtained by a process comprising the steps: selecting a plant wax, reacting the wax esters from the wax or a reactive derivative of those wax esters with glycerol or with a reactive glycerol derivative, purifying and recovering the obtained triglycerides, optionally admixing the product with a triglyceride fat such that the mixture complies with the above fat definition.

Abstract: Some Gate Arrays and in particular Filed Programmable Gate Arrays (FPGAs), realize combinatorial logic by utilizing so-called “Look Up Tables” (LUTs). Unfortunaltely the circuit expenditure for a LUT is exponentially increasing with the number of inputs. The invention overcomes this problem by using a set of gates as AND, NAND, OR, NOR, XOR, XNOR, AND/OR combination gate, AND/NOR combination gate, OR/AND combination gate, OR/NAND combination gate, identity comparator between two vectors, multiplexer and adder. In addition, conventional GAs and FPGAs utilize routing structures and channels that allow a so-called Manhattan routing. This has the disadvantage that the signal delay on such a connection is highly dependent on the number of serially linked sections. Consequently, the delay time fluctuates significantly on different connections. The invention overcomes this problem by using a X/Y routing structure with a fixed number of connection points and a fixed local routing.

Abstract: The present invention shows a high speed ADC which can be implemented easily and with low cost into a pure digital integrated circuit. This is realized by converting the analog input voltage into a pulse signal and measuring the pulse signal in length with the help of a delay line and an edge detector. With an XOR gate the input pulse can be converted into two pulses of different lengths. With a special calculation circuitry the digital output value becomes independent of the reference frequency used.

Abstract: The present invention improves an analog front-end of a Delta-Sigma analog-to-digital converter (ADC), so that by keeping the simple construction a significant improvement of the resolution is achieved. This is done by a plurality of buffers including a first buffer [5], [7] connected to the D-input of the flip-flop [4] and/or a second buffer [6], [8] connected to the output of the flip-flop on a feedback path, and a power supply different from a power supply of the semiconductor chip so that a decoupling between the semiconductor chip and the analog front-end is achieved. Additionally the frequencies at the output of the flip-flop [4] can be reduced so that the frequencies outside the semiconductor chip are much lower than the sampling clock frequency of the flip-flop [4]. So it is possible to increase the internal sampling frequency into the GigaHertz range without fearing problems in the field of EMC.

Abstract: Liquid margarines and other pourable dispersions which contain a hardstock fat derived from plant waxes. The fat consists of a mixture of triglycerides, which fat is non-hydrogenated and contains less than 10 wt. % of fatty acid residues with a chain length of 6-10 carbon atoms, of which less than 50 wt. % of the triglycerides consist of monoacyl triglycerides and which fat is characterized in that its content of fatty acid residues which are saturated and contain at least 20 carbon atoms is at least 30 wt. %, preferably at least 40 wt. % and more preferably at least 50 wt. % calculated on total fatty acid residues.

Abstract: The present invention improves the analog part of a simple Delta-Sigma A/D-Converter (analog frontend) so that by keeping the simple construction a significant improvement of the resolution is achievable.

Abstract: The invention relates to an edible composition, preferably an edible emulsion, which comprise high amounts, e.g. at least 15 mg/kg of one or more coloured carotenoids, but is not coloured in a manner as expected when using such high amounts of carotenoids, as defined by the composition having a yellowness factor of less than 4000 g/kg, and a yellowness index in the range of 1 to 90.

Abstract: Process for debittering olive oil comprising the exposure of olive oil which contains bitter polyphenols for at least 30 seconds to a finely dispersed aqueous phase, preferably consisting of hard drinking water, of which the pH is at least 5.5.