Patents by Inventor Michael Gurvitch

Michael Gurvitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8158941
    Abstract: The present invention provides a novel way of operating sensing elements or bolometers in the resistive hysteresis region of a phase-transitioning VO2 (or doped VO2) films. The invention is based on a novel principle that minor hysteresis loops inside the major loop become single-valued or non-hysteretic for sufficiently small temperature excursions. This single valued R(T) branches being characterized by essentially the same temperature coefficient of resistivity (TCR) as the semiconducting phase at room temperature. These non-hysteretic branches (NHB) can be located close to the metallic-phase end of the major loop, thus providing for tunable resistivity orders of magnitude lower than that of a pure semiconducting phase. Operating the Focal Plan Array in one of these NHBs allows for having high TCR and low resistivity simultaneously.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: April 17, 2012
    Assignee: Research Foundation of State University of New York
    Inventors: Michael A. Gurvitch, Serge Luryi, Aleksandr Y. Polyakov, Aleksandr Shabalov
  • Publication number: 20110248167
    Abstract: The present invention provides a novel way of operating sensing elements or bolometers in the resistive hysteresis region of a phase-transitioning VO2 (or doped VO2) films. The invention is based on a novel principle that minor hysteresis loops inside the major loop become single-valued or non-hysteretic for sufficiently small temperature excursions. This single valued R(T) branches being characterized by essentially the same temperature coefficient of resistivity (TCR) as the semiconducting phase at room temperature. These non-hysteretic branches (NHB) can be located close to the metallic-phase end of the major loop, thus providing for tunable resistivity orders of magnitude lower than that of a pure semiconducting phase. Operating the Focal Plan Array in one of these NHBs allows for having high TCR and low resistivity simultaneously.
    Type: Application
    Filed: October 8, 2010
    Publication date: October 13, 2011
    Inventors: Michael A. Gurvitch, Serge Luryi, Aleksandr Y. Polyakov, Aleksandr Shabalov
  • Patent number: 7326637
    Abstract: An anisotropically conductive layer ‘ACL’ for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate or membrane with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionally provide mechanical support between the flip chip and carrier so that the flip chip can undergo post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: February 5, 2008
    Assignee: Research Foundation of State University of New York
    Inventors: Sangmin Lee, Michael Gurvitch, Serge Luryi
  • Publication number: 20060186541
    Abstract: An anisotropically conductive layer ‘ACL’ for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate or membrane with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionally provide mechanical support between the flip chip and carrier so that the flip chip can undergo post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.
    Type: Application
    Filed: January 23, 2006
    Publication date: August 24, 2006
    Inventors: Sangmin Lee, Michael Gurvitch, Serge Luryi
  • Patent number: 7064432
    Abstract: An anisotropically conductive layer “ACL” (50) for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate (72) or membrane (61) with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionally provide mechanical support between the flip chip and carrier so that the flip chip can under go post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: June 20, 2006
    Assignee: The Research Foundation of State University of New York
    Inventors: Sangmin Lee, Michael Gurvitch, Serge Luryi
  • Publication number: 20040038496
    Abstract: An anisotropically conductive layer “ACL” (50) for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate (72) or membrane (61) with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionially provide mechanical support between the flip chip and carrier so that the flip chip can under go post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.
    Type: Application
    Filed: September 2, 2003
    Publication date: February 26, 2004
    Inventors: Sangmin Lee, Michael Gurvitch, Serge Luryi
  • Publication number: 20020030439
    Abstract: A display device is disclosed including a plurality of pixels arranged in a predetermined configuration. Each pixel including a mirror element disposed over a flat surface. A light modulating material disposed over the mirror element for selectively modulating a predetermined wave length of light received from an external source by transitioning between a first and a second state. The light modulating material in the first state causes destructive interference in the predetermined wave length of light and in the second state causes constructive interference in the predetermined wave length of light.
    Type: Application
    Filed: July 26, 2001
    Publication date: March 14, 2002
    Inventors: Michael Gurvitch, Maurice Halioua, Alexander Kastalsky, Sylvain Naar, Sergey Shokhor
  • Patent number: 5896005
    Abstract: A display device is disclosed including a plurality of pixels arranged in a predetermined configuration. Each pixel including a mirror element disposed over a flat surface. A light modulating material disposed over the mirror element for selectively modulating a predetermined wave length of light received from an external source by transitioning between a first and a second state. The light modulating material in the first state causes destructive interference in the predetermined wave length of light and in the second state causes constructive interference in the predetermined wave length of light.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: April 20, 1999
    Assignee: Copytele, Inc.
    Inventors: Michael Gurvitch, Maurice Halioua, Alexander Kastalsky, Sylvain Naar, Sergey Shokhor
  • Patent number: 5132280
    Abstract: A method of forming a superconductive metal oxide film on a substrate is disclosed. The method comprises depositing a metal layer on the substrate and heat treating the metal layer in an oxygen-containing atmosphere such that the oxide film is formed therefrom. The metal layer is deposited such that it is substantially free of reactive constituents, e.g., oxygen and/or fluorine, and such that it contains all the metal constitutents that are to be contained in the oxide film. Advantageously, the metal layer is deposited such that the various metal constituents (e.g., Y, Ba, and Cu) are substantially mixed. The inventive method simplifies deposition control since the densities of the metal deposits are well known and constant, and permits relatively rapid deposition (e.g., by DC sputtering) since the targets are not subject to oxidation.
    Type: Grant
    Filed: September 25, 1987
    Date of Patent: July 21, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Anthony T. Fiory, Michael Gurvitch
  • Patent number: 4837609
    Abstract: A semiconductor device which includes either a single semiconductor chip bearing an integrated circuit (IC) or two or more electrically interconnected semiconductor chips, is disclosed. This device includes interconnects between device components (on the same chip and/or on different chips), at least one of which includes a region of superconducting material, e.g., a region of copper oxide superconductor having a T.sub.c greater than about 77K. Significantly, to avoid undesirable interactions, at high processing temperatures, between the superconducting material and underlying, silicon-containing material (which, among other things, results in the superconducting material reverting to its non-superconducting state), the interconnect also includes a combination of material regions which prevents such interactions.
    Type: Grant
    Filed: September 9, 1987
    Date of Patent: June 6, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Michael Gurvitch, Roland A. Levy