Abstract: A failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT) is disclosed. The failure capture circuit includes failure detection circuitry comprising a plurality of channels and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals therefrom into failure information. A failure memory circuit and a high speed link are provided to minimize test time. The high-speed link couples the failure memory circuit to the failure detection circuitry to provide serial data transfer capability therebetween.

Abstract: A failure capture circuit for identifying failure location information from a memory-under-test (MUT) having a predetermined storage capacity is disclosed. The failure capture circuit includes failure detection circuitry adapted for coupling to the MUT and operative to apply test signals to the MUT and process output signals therefrom into failure information. The failure information is indicative of failed memory cell locations. A look-up table couples to the failure detection circuitry for storing the location information, thereby minimizing the size of the look-up table and the time to transfer failure data to a redundancy analyzer.

Abstract: A semiconductor memory manufacturing system including a tester sub-system and a redundancy analysis sub-system. The manufacturing system includes a transfer circuit between the test sub-system and the redundancy analysis sub-system that reduces the number of bits of data transferred to the redundancy analyzer. This speeds up the transfer process and also speeds up the redundancy analysis.

Abstract: Memory test apparatus including a redundancy analyzer with a catch RAM transfer interface circuit receiving fault information for a plurality of regions of a memory under test simultaneously in parallel and transmitting the information for each region to a respective one of a plurality of region modules that each has a region input circuit, a region fault RAM, and a microprocessor connected to have access to the region fault RAM, the region fault RAMs storing fault addresses identifying the locations of faults in the memory under test.