Abstract: An apparatus for allowing an add-on device to be inserted onto an active bus and configurable within one bus cycle is provided. The apparatus includes passive circuits used with a sequential multi-length pin arrangement on an I/O module. The apparatus also decouples the source of power to the I/O module from other devices on the bus which limits the disruption of power during the insertion. The I/O module limits current drawn from a backplane containing the bus which may disrupt signals during the insertion of the add-on device. And finally, the I/O module also limits bus signal disruption during insertion by precharging signal pins, increasing the resistance between the add-on I/O module pins and the backplane and adding capacitance to the bus.

Abstract: An apparatus for allowing an add-on device to be inserted onto an active bus and configurable within one bus cycle is provided. The apparatus includes passive circuits used with a sequential multi-length pin arrangement on an I/O module. The apparatus also decouples the source of power to the I/O module from other devices on the bus which limits the disruption of power during the insertion. The I/O module limits current drawn from a backplane containing the bus which may disrupt signals during the insertion of the add-on device. And finally, the I/O module also limits bus signal disruption during insertion by precharging signal pins, increasing the resistance between the add-on I/O module pins and the backplane and adding capacitance to the bus.

Abstract: A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus.