Abstract: A current switching cell for a digital to analog converter. The switching cell includes three stages, a first control stage, a data stage, and a second control stage. The first control stage is configured to either disconnect the outputs of the digital to analog converter, or to connect them to the outputs of the data stage. The data stage is configured to operate in one of two states, depending on a data signal received, and the second control stage is configured to selectively invert the output of the digital to analog converter. The two control stages may be driven with several combinations of control waveforms to implement a non return to zero mode, a return to zero mode, inverse non return to zero mode, and inverse return to zero mode.

Abstract: A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

Abstract: An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in the output signal. The second circuit includes a bootstrapping circuit adapted to regulate the voltages across any transistors in the signal path such that the voltages remain constant. In an illustrative embodiment, the second circuit bootstraps the voltages across a PMOS current source that acts as the load to an input stage, as well as a Darlington pair in an output stage of the amplifier.