Patents by Inventor Michael H. M. Chu

Michael H. M. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9558131
    Abstract: An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Jeffrey Schulz, Chiakang Sung, Michael H. M. Chu
  • Patent number: 9343124
    Abstract: A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 17, 2016
    Assignee: Altera Corporation
    Inventors: Caroline Ssu-Min Chen, Jeffrey Schulz, Michael H. M. Chu, Ravish Kapasi
  • Patent number: 9208109
    Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 8, 2015
    Assignee: Altera Corporation
    Inventors: Michael H. M. Chu, Jeffrey Schulz, Chiakang Sung, Ravish Kapasi
  • Patent number: 9032162
    Abstract: An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: Ching-Chi Chang, Ravish Kapasi, Jeffrey Schulz, Michael H. M. Chu, Caroline Ssu-Min Chen, Chiakang Sung
  • Patent number: 8671303
    Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 11, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu
  • Patent number: 8122275
    Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: February 21, 2012
    Assignee: Altera Corporation
    Inventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu
  • Patent number: 7990786
    Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: August 2, 2011
    Assignee: Altera Corporation
    Inventors: Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke, Manoj B. Roge
  • Patent number: 7990783
    Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: August 2, 2011
    Assignee: Altera Corporation
    Inventors: Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu
  • Patent number: 7983094
    Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Yan Chong
  • Patent number: 7928770
    Abstract: I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: April 19, 2011
    Assignee: Altera Corporation
    Inventors: Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong, Michael H. M. Chu, Manoj B. Roge
  • Patent number: 7876630
    Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: January 25, 2011
    Assignee: Altera Corporation
    Inventors: Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu
  • Patent number: 7706996
    Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: April 27, 2010
    Assignee: Altera Corporation
    Inventors: Yan Chong, Chiakang Sung, Joseph Huang, Michael H. M. Chu
  • Patent number: 7593273
    Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: September 22, 2009
    Assignee: Altera Corporation
    Inventors: Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke, Manoj B. Roge
  • Patent number: 7590008
    Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: September 15, 2009
    Assignee: Altera Corporation
    Inventors: Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Yan Chong
  • Patent number: 7589556
    Abstract: Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 15, 2009
    Assignee: Altera Corporation
    Inventors: Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Joseph Huang, Michael H. M. Chu, Chiakang Sung
  • Patent number: 7509223
    Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: March 24, 2009
    Assignee: Altera Corporation
    Inventors: Yan Chong, Chiakang Sung, Joseph Huang, Michael H. M. Chu
  • Patent number: 7492185
    Abstract: The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: February 17, 2009
    Assignee: Altera Corporation
    Inventors: Joseph Huang, Chiakang Sung, Michael H. M. Chu, Yan Chong
  • Patent number: 7330051
    Abstract: The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: February 12, 2008
    Assignee: Altera Corporation
    Inventors: Joseph Huang, Chiakang Sung, Michael H. M. Chu, Yan Chong