Abstract: A virtual file system is formed configured to enable the dynamic composition of immutable file system images. A file system containing a software distribution is divided into a plurality of mutually exclusive sub-trees. Each sub-tree includes a portion of the software distribution. An immutable file system image is formed for each sub-tree. During the booting of an operating system, a virtualization engine intercedes in the boot process to mount the immutable file system images to independent directories of the root file system. Upon request the virtualization engine, during run-time, combines virtual entries corresponding to immutable file system images so as to resemble the original software distribution.

Abstract: A virtual configuration system, comprising a virtualization engine and a configuration engine, for the dynamic instantiation of configuration files is disclosed. A mechanism is disclosed that allows for transactional updates to a repository of configuration settings comprising multiple files. Configuration entries are stored in a first memory location and a copy of the entries is stored in a second memory location. A virtual configuration file that includes a virtual configuration for each entry is created and used to provide the operating system with path and location information regarding the configuration entries. Simultaneously and during run-time of the computer, the configuration entries stored in the second memory location can be modified. Once the modifications are complete, a second virtual configuration file is created referencing the configuration entries stored at the second memory location.

Abstract: A method for checkpointing a system that includes receiving a stop command by an executing thread from a master, wherein the executing thread executes an operating system, continuing execution of the executing thread until a checkpoint is reached after receiving the stop command, halting execution of the executing thread at the checkpoint, and checkpointing the system by storing a state and a snapshot of memory.

Abstract: A method for translating memory addresses in a plurality of nodes, that includes receiving a first memory access request initiated by a processor of a first node of the plurality of nodes, wherein the first memory access request comprises a process virtual address and a first memory operation, translating the process virtual address to a global system address, wherein the global system address corresponds to a physical memory location on a second node of the plurality of nodes, translating the global system address to an identifier corresponding to the second node, and sending a first message requesting the first memory operation to the second node based on the identifier, wherein the second node performs the first memory operation on the physical memory location.

Abstract: A method for executing an application on a plurality of nodes, that includes synchronizing a first clock of a first node of the plurality of nodes and a second clock of a second node of the plurality of nodes, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, wherein configuring the hypervisor comprises allocating a first number of cycles of the first clock to the first privileged domain, configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain, wherein configuring the second hypervisor that includes allocating the first number of cycles of the first clock to the second privileged domain, and executing the application in the first application domain and the second application domain, wherein the first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Abstract: A method for installing a device driver for a device in a guest domain, that includes obtaining a first device driver for the device by a hypervisor, installing, by the hypervisor, the first device driver into memory allocated to the guest domain, and notifying an operating system in the guest domain of the first device driver after installing the device driver, wherein the operating system communicates with the device using the first device driver.

Abstract: A system for mapping memory of a computer system includes a sorter, a partitioner, and a mapper. The sorter sorts a physical memory space to obtain a sorted virtual memory space, where the physical memory space includes a plurality of memory patterns, wherein each of the plurality of memory patterns is associated with a physical device and includes at least one memory block, wherein the at least one memory block is contiguous and addressable, and the plurality of memory patterns are arranged based on a predefined number of occurrences of each memory pattern, size of contiguous memory address ranges in each of the plurality of memory patterns, size of contiguous memory address ranges in each of the plurality of memory patterns, and arrangement of contiguous address ranges in each of the plurality of memory patterns.

Abstract: One embodiment of the present invention provides a system that facilitates concurrent non-transactional operations in a transactional memory system. During operation, the system receives a load instruction related to a local transaction. Next, the system determines if an entry for the memory location requested by the load instruction already exists in the transaction buffer. If not, the system allocates an entry for the memory location in the transaction buffer, reads data for the load instruction from the cache, and stores the data in the transaction buffer. Finally, the system returns the data to the processor to complete the load instruction. In this way, if a remote non-transactional store instruction is received during the transaction, the remote non-transactional store proceeds and does not cause the local transaction to abort.

Abstract: A method for detecting a dependence violation in an application that involves executing a plurality of sections of the application in parallel, and logging memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, where the plurality of logs is compared while executing the plurality of sections to determine whether the dependence violation exists.

Abstract: A system for mapping memory of a computer system includes a sorter, a partitioner, and a mapper. The sorter sorts a physical memory space to obtain a sorted virtual memory space, where the physical memory space includes a plurality of memory patterns, wherein each of the plurality of memory patterns is associated with a physical device and includes at least one memory block, wherein the at least one memory block is contiguous and addressable, and the plurality of memory patterns are arranged based on a predefined number of occurrences of each memory pattern, size of contiguous memory address ranges in each of the plurality of memory patterns, size of contiguous memory address ranges in each of the plurality of memory patterns, and arrangement of contiguous address ranges in each of the plurality of memory patterns.

Abstract: A method for committing memory transactions in an application that includes executing a plurality of sections of the application in parallel, logging a plurality of memory transactions that occur while executing the plurality of sections to obtain a plurality of logs and a plurality of temporary results, wherein the plurality of memory transactions that includes a plurality of writes to at least one memory location, comparing the plurality of logs to identify an optimal list of writes from the plurality of writes, and committing memory transactions corresponding to a subset of the plurality of temporary results, wherein the subset of the plurality of temporary results is identified by the optimal list of writes.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a main loop structure having indexing expressions based on the original loop structure is included. The indexing expressions included in the main loop preferably cannot produce an underflow or an overflow. Also included in the range check elimination loop structure is a post-loop structure based on the original loop structure that is capable of testing indexing expressions for overflow.

Abstract: Provided is a method for performing loop-unrolling optimization during program execution. In one example, a method for loop optimization within a dynamic compiler system is disclosed. A computer program having a loop structure is executed, wherein the loop structure includes a loop exit test to be performed during each loop iteration. The loop structure is compiled during the execution of the computer program, and an unrolled loop structure is created during the compiling operation. The unrolled loop structure includes plurality of loop bodies based on the original loop structure. Further, the unrolled loop structure can include the loop exit test, which can be performed once for each iteration of the plurality of loop bodies.

Abstract: A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a main loop structure having indexing expressions based on the original loop structure is included. The indexing expressions included in the main loop preferably cannot produce an underflow or an overflow. Also included in the range check elimination loop structure is a post-loop structure based on the original loop structure that is capable of testing indexing expressions for overflow.

Abstract: Provided is a method for performing loop-unrolling optimization during program execution. In one example, a method for loop optimization within a dynamic compiler system is disclosed. A computer program having a loop structure is executed, wherein the loop structure includes a loop exit test to be performed during each loop iteration. The loop structure is compiled during the execution of the computer program, and an unrolled loop structure is created during the compiling operation. The unrolled loop structure includes plurality of loop bodies based on the original loop structure. Further, the unrolled loop structure can include the loop exit test, which can be performed once for each iteration of the plurality of loop bodies.

Abstract: Methods and apparatus for providing a substantially full set of state information to a debugger, without significantly compromising system performance, in order to debug optimized computer program code are disclosed. According to one aspect of the present invention, a method for obtaining information associated with program code includes adding a segment of code, which includes a representation that is effectively not used after it is computed, to the program code. Debugging code is added in proximity to the segment of code, and machine code is generated from the program code. The machine code includes a break point that is associated with the debugging code, and includes an instruction at the breakpoint. Finally, the method includes replacing the instruction at the break point with a branch instruction that is arranged to cause the debugging code to execute.