Abstract: A system is provided that detects a card skimmer in a target system, wherein the card skimmer surreptitiously gathers credit/debit card information during operation of the target system. This system first gathers target electromagnetic interference (EMI) signals by monitoring EMI signals generated by the target system through an external scanner with a directional antenna. Next, the system generates a target EMI fingerprint from the target EMI signals. The system then compares the target EMI fingerprint against a reference EMI fingerprint for the target system to determine whether the target system contains a card skimmer.

Abstract: The disclosed embodiments provide a system that detects unwanted electronic components in a target computing system. During operation, the system obtains target electromagnetic interference (EMI) signals, which were gathered by monitoring EMI signals generated by the target computing system, using an insertable device, wherein when the insertable device is inserted into the target computing system, the insertable device gathers the target EMI signals from the target computing system. Next, the system generates a target EMI fingerprint from the target EMI signals. Finally, the system compares the target EMI fingerprint against a reference EMI fingerprint for the target computing system to determine whether the target computing system contains any unwanted electronic components.

Abstract: The disclosed embodiments provide a system that detects unwanted electronic components in a target asset. During operation, the system generates a sinusoidal load for the target asset. Next, the system obtains target electromagnetic interference (EMI) signals by monitoring EMI signals generated by the target asset while the target asset is executing the sinusoidal load. The system then generates a target EMI fingerprint from the target EMI signals. Finally, the system compares the target EMI fingerprint against a reference EMI fingerprint for the target asset to determine whether the target asset contains unwanted electronic components.

Abstract: The disclosed embodiments provide a system that detects execution of malicious cryptomining software in a target computing system. During operation, the system monitors target electromagnetic interference (EMI) signals generated during operation of the target computing system. Next, the system generates a target EMI fingerprint from the target EMI signals. The system then compares the target EMI fingerprint against a set of malicious EMI fingerprints for different pieces of malicious cryptomining software to determine whether the target computing system is executing malicious cryptomining software.

Abstract: The disclosed embodiments provide a system that detects unwanted electronic components in a target asset. During operation, the system generates a sinusoidal load for the target asset. Next, the system obtains target electromagnetic interference (EMI) signals by monitoring EMI signals generated by the target asset while the target asset is executing the sinusoidal load. The system then generates a target EMI fingerprint from the target EMI signals. Finally, the system compares the target EMI fingerprint against a reference EMI fingerprint for the target asset to determine whether the target asset contains unwanted electronic components.

Abstract: A method for constructing a ramp-stacked chip assembly starts by obtaining a set of semiconductor chips, including a first chip and a set of additional chips. Next, the method stacks the set of additional chips one at a time over the first chip, wherein each additional chip is horizontally offset from a preceding additional chip to form a ramp-stack. While stacking each additional chip, the method: applies an adhesive layer to a surface of a preceding chip in the ramp-stack; and uses a vacuum tool to pick up the additional chip and place the additional chip on the adhesive layer of the preceding chip. During this pick-and-place process, the vacuum tool spans most of a surface of the additional chip and also provides planar support for the additional chip, which causes a holding force of the vacuum tool to flatten the additional chip prior to placement on the preceding chip.

Abstract: The disclosed embodiments provide a system that detects execution of malicious cryptomining software in a target computing system. During operation, the system monitors target electromagnetic interference (EMI) signals generated during operation of the target computing system. Next, the system generates a target EMI fingerprint from the target EMI signals. The system then compares the target EMI fingerprint against a set of malicious EMI fingerprints for different pieces of malicious cryptomining software to determine whether the target computing system is executing malicious cryptomining software.

Abstract: A method for constructing a ramp-stacked chip assembly starts by obtaining a set of semiconductor chips, including a first chip and a set of additional chips. Next, the method stacks the set of additional chips one at a time over the first chip, wherein each additional chip is horizontally offset from a preceding additional chip to form a ramp-stack. While stacking each additional chip, the method: applies an adhesive layer to a surface of a preceding chip in the ramp-stack; and uses a vacuum tool to pick up the additional chip and place the additional chip on the adhesive layer of the preceding chip. During this pick-and-place process, the vacuum tool spans most of a surface of the additional chip and also provides planar support for the additional chip, which causes a holding force of the vacuum tool to flatten the additional chip prior to placement on the preceding chip.

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Abstract: A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Abstract: A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.