Abstract: The present invention relates to a improved process for the biotechnological production of compounds for which ribose-5-phosphate, ribulose-5-phosphate or xylulose-5-phosphate is biosynthetic precursor like riboflavin (vitamin B2), FAD, FMN, pyridoxal phosphate (vitamin B6), guanosine, GMP, adenosine, AMP. The invention further pertains to the generation of the organism producing those compounds. It furthermore relates to the generation of mutated transketolases that allow normal growth on glucose but reduced growth on gluconate when introduced into the production strains and to polynucleotides encoding them.

Abstract: A photosensitive drum for a printer cartridge, which can be easily mounted on a printer cartridge of which the positions of drum connectors are fixed, is disclosed. The photosensitive drum for a printer cartridge comprises a cylindrical drum having a photosensitive layer on a cylindrical surface thereof; and a pair of rotation shafts which is respectively mounted on the sides of the cylindrical drum for rotating and supporting the cylindrical drum, wherein at least one of the rotation shafts is insert-fitted to the side of the cylindrical drum.

Abstract: Disclosed herein are novel DNA constructs encoding dihydrodipicolinic acid synthase that are useful for generating transgenic events. Also provided are transgenic plants harboring such DNA constructs, the expression of which results in increased lysine in the plant or plant product. Also provided are maize plants having LY038 Event and progeny thereof having this event. Additionally disclosed are assays for detecting the presence of a lysine-increasing transgenic event based on the DNA sequence of the exogenous DNA construct inserted into the maize genome and of genomic sequences flanking the insertion site.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Abstract: An improved NAND-type memory cell structure having improved reliability and endurance. Since a high risk area for oxide breakdown and/or current leakage exists in the tunnel oxide layer, source/drain overlap region, the present invention provides a NAND-type memory cell fabricated using controlled formation of the tunnel oxide layer.

Abstract: A method utilizes a keyword based rule set to crawl through the web pages and fetch the related product prices. There are many algorithms involved for accurately matching and selecting the required items. The data is then sorted by the price and brand and compared with the database of a group of known products. The prices of the known products are then adjusted via a set of built-in rules to put them in a very competitive position, such as number 1 or 2 among the same product category. The new prices make the seller's products very competitive online. The new price list will then automatically be posted to the web server to replace the old prices. The whole process is automated by simply placing the program on a computer operating system scheduler and let it run periodically according to the specified date and time.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Abstract: An abrasive diamond composite formed from coated diamond particles and a matrix material. The diamonds have a protective coating formed from a refractory material having a composition MCxNy, that prevents corrosive chemical attack of the diamonds by the matrix material. The abrasive diamond composite may further include an infiltrant, such as a braze material. Alternatively, the abrasive diamond composite may include a plurality of coated diamond particles and a braze material filling interstitial spaces between the coated diamond particles. Methods of making such abrasive diamond composites are also disclosed.

Abstract: A hard material layer deposited on a hard metal work piece is removed by electrolytic passivation in which a maximum current density equal to at least 0.01 A/cm2 is generated on the work piece at the beginning of the layer removal process. The hard material layer rapidly flakes off without causing substantial damage to the hard metal material located underneath.

Abstract: An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell during its programming. In one embodiment, the NAND array structure includes a buried layer at a junction between the substrate and a well in which the memory cells are formed. Programming is achieved using hot electron injection. In one embodiment, multiple memory cells are programmed simultaneously.

Abstract: A vacuum coating installation has at least a central distribution station which can be evacuated and has a transport arrangement driven in a controlled manner essentially along a plane, for the material to be treated. One operating station for the distribution station as well as at least two processing stations for the material to be treated are provided. The three or more stations communicate by way of operating openings with the distribution station, through which openings the material to be treated can be transported from one station into the other by the transport arrangement for the material to be treated. The material to be treated is formed by individual workpiece holders of the installation, each having a plurality of workpiece supports.

Abstract: A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85 Å-105 Å. For single tunnel gate approach, a careful selection of the medium doped source/drain region implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentrations of 1013-1014/cm2.

Abstract: An abrasive diamond composite formed from coated diamond particles and a matrix material. The diamonds have a protective coating formed from a refractory materia1 having a composition MCxNy, that prevents corrosive chemical attack of the diamonds by the matrix material. The abrasive diamond composite may further include an infiltrant, such as a braze material. Alternatively, the abrasive diamond composite may include a plurality of coated diamond particles and a braze material filling interstitial spaces between the coated diamond particles. Methods of making such abrasive diamond composites are also disclosed.

Abstract: Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.

Abstract: A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.

Abstract: An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Abstract: A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.