Abstract: A case having an ultrasonic seal around a record, wherein the case is capable of displaying one or multiple records in a linear arrangement. The disc display case includes a disc case having a first base plate mounted to a disc plate, wherein the disc case includes an ultrasonic seal and can house a vinyl record. In some embodiments, an album case, formed by a second base plate mounted to an album plate, is connected to the disc case to form a side-to-side arrangement. The album case can house an album cover. In some embodiments, the album case is designed to receive a double album cover instead of a single album cover to accommodate a thicker, double album cover. In some embodiments, the disc case and the album case are pivotally connected to one another.

Abstract: A foldable case having an ultrasonic seal around a record, wherein the case is capable of displaying one or multiple records in a linear arrangement. The foldable disc display case includes a disc case having a first base plate mounted to a disc plate, wherein the disc case includes an ultrasonic seal and can house a vinyl record. An album case, formed by a second base plate mounted to an album plate, is pivotally connected to the disc case via a hinge to form a side-to-side arrangement. The album case can house an album cover. In some embodiments, the album case is designed to receive a double album cover instead of a single album cover to accommodate a thicker, double album cover. A hinge spacer is mounted between the hinge and the base plates to allow the disc case and the album case to be coplanar with one another.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio ?3/?ref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio ?3/?ref are substantially independent of the divider ratio N.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A turf manicuring apparatus for enabling dragging of a drag tool such as a net behind a tractor operating across a turf. The apparatus comprises (a) a frame including a rod longitudinally centered about an axis, at least one lift member extending transversely from the rod, and a device for suspending a drag tool from the rod; (b) at least one support member connectable to the tractor and extending away from the tractor to form a receptacle adapted to receive the rod and allow rotation of the rod about the axis, with the support member being adapted to support the frame in an elevated position rearward of the tractor so that the rod is disposed transverse to the direction of movement in a plane substantially parallel with the turf beneath the tractor; (c) a device for rotating the frame about the axis, thus raising and lowering the lift member; and (d) an actuator controllably connected to the device for rotating.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio &ohgr;3/&ohgr;ref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio &ohgr;3/&ohgr;ref are substantially independent of the divider ratio N.

Abstract: Disclosed herein is a turf manicuring apparatus for enabling more efficient dragging of a drag tool such as a net behind a tractor operating across a turf.

Abstract: A single chip dual function 10 Base-T/100 Base-X physical layer interface device (PHY) compatible with existing 5 V parts is provided. The PHY includes a media-independent interface (MII) and connects to an unshielded twisted pair cable via an isolation transformer and a single RJ45 connector. The PHY includes built-in auto-negotiation circuitry that allows for automatic selection of half/full duplex 10 Base-T and 100 Base-TX, while auto-polarity correction circuitry ensures immunity to receive pair reversal in the 10 Base-T mode of operation. The PHY includes internal PLL circuitry that uses a single 20 MHz clock or crystal, but that is suitable for either speed mode. The PHY includes low-power and power down modes. The 10 Base-T portions of the PHY include smart squelch for improved receive noise immunity. The PHY includes high jitter tolerance clock recovery circuitry and transmit jabber detection circuitry. The 10 Base-T portions of the PHY include on board transmit waveshaping.

Abstract: Incoming data which is required to be passed to a desired storage location under the control of a processor is received by a store prior to being passed to a serial communications controller. The store is preferably a FIFO store and stores the data at an incoming data rate determined by the incoming transmission line data rate and feeds the data to the serial communications controller at a higher data rate under the control of a clock generator which is energized by control circuitry only when the serial communications controller indicates that it is able to accept the data. The processor can therefore control the serial communications controller to cease to process incoming data, which data is then stored until the processor can spare the time to recommence processing the incoming data.