Patents by Inventor Michael Haverty
Michael Haverty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20260123371Abstract: A method and corresponding device structure includes depositing a metal fill material on at least one electrical connection formed in a feature formed within a first dielectric layer of a semiconductor device structure, wherein the metal fill material completely fills the feature. The method further includes depositing a protective layer over an upper surface of the metal fill material, and depositing a barrier layer over the protective layer.Type: ApplicationFiled: October 28, 2024Publication date: April 30, 2026Inventors: Muthukumar KALIAPPAN, Avgerinos V. GELATOS, Michael HAVERTY, Aaron Michael DANGERFIELD, Shinjae HWANG, Zhiyuan WU
-
Patent number: 12568803Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.Type: GrantFiled: March 3, 2023Date of Patent: March 3, 2026Assignee: Applied Materials, Inc.Inventors: Muthukumar Kaliappan, Bhaskar Jyoti Bhuyan, Yong Jin Kim, Carmen Leal Cervantes, Xiangjin Xie, Jesus Candelario Mendoza-Gutierrez, Aaron Dangerfield, Michael Haverty, Mark Saly, Kevin Kashefi
-
Patent number: 12550643Abstract: Novel cyclic silicon precursors and oxidants are described. Methods for depositing silicon-containing films on a substrate are described. The substrate is exposed to a silicon precursor and a reactant to form the silicon-containing film (e.g., elemental silicon, silicon oxide, silicon nitride). The exposures can be sequential or simultaneous.Type: GrantFiled: June 22, 2021Date of Patent: February 10, 2026Assignees: Applied Materials, Inc., National University of SingaporeInventors: Chandan Kr Barik, Doreen Wei Ying Yong, John Sudijono, Cong Trinh, Bhaskar Jyoti Bhuyan, Michael Haverty, Muthukumar Kaliappan, Yingqian Chen, Anil Kumar Tummanapelli, Richard Ming Wah Wong
-
Publication number: 20260026326Abstract: Methods of depositing a liner layer in a semiconductor device are described. In some embodiments, the method includes depositing a carbon layer including carbon on a substrate, the substrate having at least one feature including a sidewall surface and the carbon layer having a carbon surface; and selectively depositing the liner layer on the sidewall surface over the carbon surface. In other embodiments, the method includes depositing a carbon layer comprising carbon in a bottom second portion of a substrate feature selectively over a top first portion of the substrate feature, the top first portion having a sidewall surface, the carbon layer having a carbon surface; etching the carbon surface; and depositing the conformal layer on the sidewall surface of the top first portion, the conformal layer deposited on the sidewall surface selectively over the carbon surface.Type: ApplicationFiled: July 17, 2024Publication date: January 22, 2026Applicant: Applied Materials, Inc.Inventors: Vamshi Krishna Gaddamedi, Abdul Aziz Khaja, Ligang Gao, Karthik Colinjivadi, Muthukumar Kaliappan, Vahid Ghodsi Karbasdehi, Michael Haverty
-
Patent number: 12500080Abstract: Embodiments include semiconductor processing methods to form low-? films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system. The one or more deposition precursors may include a silicon-containing precursor that may be a cyclic compound. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.Type: GrantFiled: August 26, 2022Date of Patent: December 16, 2025Assignee: Applied Materials, Inc.Inventors: Shruba Gangopadhyay, Bhaskar Jyoti Bhuyan, Michael Haverty, Bo Xie, Li-Qun Xia, Rui Lu, Yijun Liu, Ruitong Xiong, Xiaobo Li, Lakmal C. Kalutarage, Lauren Bagby
-
Publication number: 20250313950Abstract: Disclosed herewith are a precursor, a gas mixture, and a method for depositing a dielectric film in a processing chamber. A method includes disposing a substrate on a susceptor disposed within a processing chamber; controlling a pressure level and a temperature of the processing chamber; delivering an RF power into the processing chamber; providing a precursor-containing gas mixture into the processing chamber, and applying a post-deposition process to the substrate after the dielectric film is formed on the substrate. The precursor-containing gas mixture includes a precursor and an inert gas selected from the group consisting of argon, nitrogen, and helium. The precursor includes a carbosilane having a Si—C—Si structure in a backbone of the precursor.Type: ApplicationFiled: April 8, 2025Publication date: October 9, 2025Inventors: Lakmal C. KALUTARAGE, Lauren Mary BAGBY, Michael HAVERTY, Bo XIE, Chi-I LANG, Bhaskar SOMAN, Rui LU, Kent Qiujing ZHAO, Li-Qun XIA, Shankar VENKATARAMAN
-
Publication number: 20250299944Abstract: Chalcogen silane precursors having electron withdrawing groups are described. Methods for depositing one or more of a silicon nitride (SixNy) film, a silicon oxide (SiOx) film, or a silicon oxynitride (SiOxNz) on a substrate are described. The substrate is exposed to the chalcogen silane precursor and a reactant to deposit the silicon nitride (SixNy) film, the silicon oxide (SiOx) film, and/or the silicon oxynitride (SiOxNz) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).Type: ApplicationFiled: March 19, 2024Publication date: September 25, 2025Applicants: Applied Materials, Inc., National University of SingaporeInventors: Zhijie Chua, Chandan Kr Barik, John Sudijono, Bhaskar Jyoti Bhuyan, Michael Haverty, Muthukumar Kaliappan, Sao Chuan Yeh, Anil Kumar Tummanapelli, Yingqian Chen, Richard Ming Wah Wong
-
Publication number: 20250270693Abstract: A method includes depositing a contact capping layer over a surface of a contact structure, the contact capping layer deposition process comprising flowing hydrogen (H2) and a silicon containing gas into a processing chamber, and delivering a molybdenum (Mo) precursor for a first period of time and halting delivering of the Mo precursor for a second period of time while flowing the hydrogen (H2) and the silicon containing gas, and repeating delivering the Mo precursor and halting delivering the Mo precursor one or more times while flowing the hydrogen (H2) and the silicon containing gas.Type: ApplicationFiled: February 28, 2024Publication date: August 28, 2025Inventors: Muthukumar KALIAPPAN, Yang HU, Michael HAVERTY, Avgerinos V. GELATOS
-
Patent number: 12281382Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.Type: GrantFiled: May 24, 2023Date of Patent: April 22, 2025Assignee: Applied Materials, Inc.Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Aaron Dangerfield, Feng Q. Liu, Mark Saly, Michael Haverty, Muthukumar Kaliappan
-
Publication number: 20250125157Abstract: The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).Type: ApplicationFiled: April 12, 2024Publication date: April 17, 2025Inventors: Michael HAVERTY, Avgerinos V. GELATOS, Gaurav THAREJA, Lauren Mary BAGBY, Lakmal C. KALUTARAGE, Jeffrey W. ANTHIS, Archana KUMAR
-
Publication number: 20250046600Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as finFETs, GAAs, and the like, without creating a seam. The methods include selective deposition processes using blocking compounds in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.Type: ApplicationFiled: July 31, 2023Publication date: February 6, 2025Applicant: Applied Materials, Inc.Inventors: Muthukumar Kaliappan, Zhebo Chen, Michael Haverty, Yongjing Lin, Shih Chung Chen, Gang Shen, Alexander Jansen, Janardhan Devrajan
-
Patent number: 12142477Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).Type: GrantFiled: April 14, 2023Date of Patent: November 12, 2024Assignee: Applied Materials, Inc.Inventors: Chandan Kr Barik, Michael Haverty, Muthukumar Kaliappan, Cong Trinh, Bhaskar Jyoti Bhuyan, John Sudijono, Anil Kumar Tummanapelli, Richard Ming Wah Wong, Yingqian Chen
-
Patent number: 12141688Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately ?0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.Type: GrantFiled: July 20, 2021Date of Patent: November 12, 2024Assignee: Applied Materials, Inc.Inventors: Milan Pesic, Shruba Gangopadhyay, Muthukumar Kaliappan, Michael Haverty
-
Publication number: 20240363337Abstract: Semiconductor processing methods are described for forming low-? dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.Type: ApplicationFiled: April 26, 2023Publication date: October 31, 2024Applicant: Applied Materials, Inc.Inventors: Muthukumar Kaliappan, Bo Xie, Shanshan Yao, Li-Qun Xia, Michael Haverty, Rui Lu, Xiaobo Li, Chi-I Lang, Shankar Venkataraman
-
Publication number: 20240355675Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule, such as a boron-containing compound, to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.Type: ApplicationFiled: April 9, 2024Publication date: October 24, 2024Applicant: Applied Materials, Inc.Inventors: Muthukumar Kaliappan, Yong Jin Kim, Carmen Leal Cervantes, Bhaskar Jyoti Bhuyan, Xiangjin Xie, Michael Haverty, Kevin Kashefi, Mark Saly, Aaron Dangerfield, Jesus Candelario Mendoza-Gutierrez
-
Publication number: 20240297073Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.Type: ApplicationFiled: March 3, 2023Publication date: September 5, 2024Applicant: Applied Materials, Inc.Inventors: Muthukumar Kaliappan, Bhaskar Jyoti Bhuyan, Yong Jin Kim, Carmen Leal Cervantes, Xiangjin Xie, Jesus Candelario Mendoza-Gutierrez, Aaron Dangerfield, Michael Haverty, Mark Saly, Kevin Kashefi
-
Publication number: 20240087881Abstract: Embodiments include semiconductor processing methods to form low-K films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system, wherein the one or more deposition precursors include a silicon-containing precursor. The silicon-containing precursor may include a carbon chain. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.Type: ApplicationFiled: August 26, 2022Publication date: March 14, 2024Applicant: Applied Materials, Inc.Inventors: Michael Haverty, Shruba Gangopadhyay, Bo Xie, Yijun Liu, Ruitong Xiong, Rui Lu, Xiaobo Li, Li-Qun Xia, Lakmal C. Kalutarage, Lauren Bagby
-
Publication number: 20240087880Abstract: Embodiments include semiconductor processing methods to form low-? films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system. The one or more deposition precursors may include a silicon-containing precursor that may be a cyclic compound. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.Type: ApplicationFiled: August 26, 2022Publication date: March 14, 2024Applicant: Applied Materials, Inc.Inventors: Shruba Gangopadhyay, Bhaskar Jyoti Bhuyan, Michael Haverty, Bo Xie, Li-Qun Xia, Rui Lu, Yijun Liu, Ruitong Xiong, Xiaobo Li, Lakmal C. Kalutarage, Lauren Bagby
-
Publication number: 20240071927Abstract: Methods of forming interconnects and electronic devices are described. Methods of forming interconnects include forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and exposing the tantalum nitride layer and ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum doped ruthenium layer thereon. Apparatuses for performing the methods are also described.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Shinjae Hwang, Feng Chen, Muthukumar Kaliappan, Michael Haverty
-
Patent number: 11821070Abstract: Methods of depositing metal films comprising exposing a substrate surface to a first metal precursor followed by a non-oxygen containing reducing agent comprising a second metal to form a zero-valent first metal film are described. The reducing agent has a metal center that is more electropositive than the metal center of the first metal precursor. In some embodiments, methods of depositing ruthenium films are described in which a substrate surface is exposed to a ruthenium precursor to form a ruthenium containing film on the substrate surface followed by exposure to a non-oxygen containing reducing agent to reduce the ruthenium containing film to a zero-valent ruthenium film and generate an oxidized form of the reducing agent.Type: GrantFiled: November 11, 2020Date of Patent: November 21, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Nasrin Kazem, Muthukumar Kaliappan, Jeffrey W. Anthis, Michael Haverty