Abstract: A host computer has a plurality of containers including a first container executing therein, where the host also includes a physical network interface controller (NIC). A packet handling interrupt is detected upon receipt of a first data packet associated with the first container If the first virtual machine is latency sensitive, then the packet handling interrupt is processed. If the first virtual machine is not latency sensitive, then the first data packet is queued and processing of the packet handling interrupt is delayed.

Abstract: A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.

Abstract: A host computer has a plurality of virtual machines executing therein under the control of a hypervisor, where the host also includes a physical network interface controller (NIC). An interrupt controller detects an interrupt generated by the physical NIC, where the interrupt corresponds to a virtual machine. If the virtual machine has exclusive affinity to one or more physical central processing units (CPUs), then the interrupt is forwarded to the virtual machine. If the virtual machine does not have exclusive affinity, then a process in the hypervisor is invoked to forward the interrupt to the virtual machine.

Abstract: A host computer has a virtualization software that supports execution of a plurality of virtual machines, where the virtualization software includes a virtual machine monitor for each of the virtual machines, and where each virtual machine monitor emulates a virtual central processing unit (CPU) for a corresponding virtual machine. A virtual machine monitor halts execution of a virtual CPU of a virtual machine by receiving a first halt instruction from a corresponding virtual machine and determining whether the virtual machine is latency sensitive. If the virtual machine is latency sensitive, then a second halt instruction is issued from the virtual machine monitor to halt a physical CPU on which the virtual CPU executes. If the virtual machine is not latency sensitive, then a system call to a kernel executing on the host computer is executed to indicate to the kernel that the virtual CPU is in an idle state.

Abstract: A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.

Abstract: A host computer has a virtualization software that supports execution of a plurality of virtual machines, where the virtualization software includes a virtual machine monitor for each of the virtual machines, and where each virtual machine monitor emulates a virtual central processing unit (CPU) for a corresponding virtual machine. A virtual machine monitor halts execution of a virtual CPU of a virtual machine by receiving a first halt instruction from a corresponding virtual machine and determining whether the virtual machine is latency sensitive. If the virtual machine is latency sensitive, then a second halt instruction is issued from the virtual machine monitor to halt a physical CPU on which the virtual CPU executes. If the virtual machine is not latency sensitive, then a system call to a kernel executing on the host computer is executed to indicate to the kernel that the virtual CPU is in an idle state.

Abstract: A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.

Abstract: The current document is directed to methods and systems for monitoring the performance of memory management in virtual machines. By accurately measuring the performance of memory management in virtual machines, a virtualization layer can dynamically reconfigure virtual machines to use more optimal memory-management methods, intelligently schedule execution of virtual machines to increase memory-management performance, and migrate virtual machines among different servers and computer systems to increase memory-management performance.

Abstract: The current document is directed to virtualized PMUs provided by virtualization layers. The currently disclosed virtualized PMUs are decoupled from the underlying PMU hardware features of processors on which the virtualization layer executes. The decoupling is achieved, in part, by time multiplexing the underlying hardware PMU registers to provide a greater number of virtualized PMU registers than the number of hardware-PMU registers provided by at least some of the underlying hardware PMUs. The decoupling is also achieved by providing for monitoring, by the virtualized PMU registers, of computed processor events and approximated processor events in addition to the processor events monitored by the underlying hardware PMUs.

Abstract: Methods, apparatus, and articles of manufacture to virtualize performance counters are disclosed. An example method includes dividing performance events to be counted into a plurality of classes; assigning a first virtual performance counter of a virtual machine to a first performance event type in a first one of the classes; assigning a second virtual performance counter of the virtual machine to a second performance event type in a second one of the classes different from the first class; incrementing the first virtual performance counter in response to a first occurrence of the first performance event type during direct execution of guest instructions by the virtual machine; and not incrementing the first virtual performance counter in response to a second occurrence of the first performance event type during execution of emulated instructions by a hypervisor on behalf of the virtual machine.

Abstract: A host computer has a virtualization software that supports execution of a plurality of virtual machines, where the virtualization software includes a virtual machine monitor for each of the virtual machines, and where each virtual machine monitor emulates a virtual central processing unit (CPU) for a corresponding virtual machine. A virtual machine monitor halts execution of a virtual CPU of a virtual machine by receiving a first halt instruction from a corresponding virtual machine and determining whether the virtual machine is latency sensitive. If the virtual machine is latency sensitive, then a second halt instruction is issued from the virtual machine monitor to halt a physical CPU on which the virtual CPU executes. If the virtual machine is not latency sensitive, then a system call to a kernel executing on the host computer is executed to indicate to the kernel that the virtual CPU is in an idle state.

Abstract: A host computer has one or more physical central processing units (CPUs) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical CPU when the corresponding container is determined to be latency sensitive. The assignment of a process to execute exclusively on a corresponding physical CPU includes the migration of tasks from the corresponding physical CPU to one or more other physical CPUs of the host system, and the directing of task and interrupt processing to the one or more other physical CPUs. Tasks of the process corresponding to the container are then executed on the corresponding physical CPU.

Abstract: A host computer has a plurality of containers including a first container executing therein, where the host also includes a physical network interface controller (NIC). A packet handling interrupt is detected upon receipt of a first data packet associated with the first container. If the first virtual machine is latency sensitive, then the packet handling interrupt is processed. If the first virtual machine is not latency sensitive, then the first data packet is queued and processing of the packet handling interrupt is delayed.

Abstract: A host computer has a plurality of virtual machines executing therein under the control of a hypervisor, where the host also includes a physical network interface controller (NIC). An interrupt controller detects an interrupt generated by the physical NIC, where the interrupt corresponds to a virtual machine. If the virtual machine has exclusive affinity to one or more physical central processing units (CPUs), then the interrupt is forwarded to the virtual machine. If the virtual machine does not have exclusive affinity, then a process in the hypervisor is invoked to forward the interrupt to the virtual machine.

Abstract: Methods, apparatus, and articles of manufacture to virtualize performance counters are disclosed. An example method includes scheduling a virtual machine on a processor, incrementing a virtual performance counter in response to an occurrence of a speculative event during direct execution of guest instructions by the virtual machine on the processor, and incrementing the virtual performance counter in response to an occurrence of the speculative event during execution of emulated instructions by a hypervisor on behalf of the virtual machine on the processor.

Abstract: The invention is directed to instrumenting object code of an application and/or an operating system on a target machine so that execution trace data can be generated, collected, and subsequently analyzed for various purposes, such as debugging and performance. Automatic instrumentation may be performed on an application's object code before, during or after linking. A target machine's operating system's object code can be manually or automatically instrumented. By identifying address space switches and thread switches in the operating system's object code, instrumented code can be inserted at locations that enable the execution trace data to be generated. The instrumentation of the operating system and application can enable visibility of total system behavior by enabling generation of trace information sufficient to reconstruct address space switches and context switches.

Abstract: The invention is directed to instrumenting object code of an application and/or an operating system on a target machine so that execution trace data can be generated, collected, and subsequently analyzed for various purposes, such as debugging and performance. Automatic instrumentation may be performed on an application's object code before, during or after linking. A target machine's operating system's object code can be manually or automatically instrumented. By identifying address space switches and thread switches in the operating system's object code, instrumented code can be inserted at locations that enable the execution trace data to be generated. The instrumentation of the operating system and application can enable visibility of total system behavior by enabling generation of trace information sufficient to reconstruct address space switches and context switches.

Abstract: We have developed a high through-put screen capable of isolating inhibitors of polypeptide aggregation, such as Alzheimer's Disease polypeptide A? aggregation, or other disease state aggregating proteins, from amidst large libraries of candidate inhibitors. The screen uses a fusion of a polypeptide domain that self-aggregates, such as an A?42 domain characteristic of Alzheimer's disease plaques, to a reporter construct, such as Green Fluorescent Protein (GFP) or similar fluorescent protein. In the absence of inhibition, the rapid misfolding and aggregation of A?42 causes the entire fusion protein to misfold, thereby preventing fluorescence. Compounds that inhibit A?42 aggregation enable GFP to fold into its native structure, and can be identified by the resulting fluorescent signal.

Abstract: The present invention provides a quadrupole mass spectrometer and an ion filter for use in the quadrupole mass spectrometer. The ion filter includes a thin patterned layer including a two-dimensional array of poles forming one or more quadrupoles. The patterned layer design permits the use of very short poles and with a very dense spacing of the poles, so that the ion filter may be made very small. Also provided is a method for making the ion filter and the quadrupole mass spectrometer. The method involves forming the patterned layer of the ion filter in such a way that as the poles of the patterned layer are formed, they have the relative positioning and alignment for use in a final quadrupole mass spectrometer device.

Abstract: The present invention provides a quadrupole mass spectrometer and an ion filter for use in the quadrupole mass spectrometer. The ion filter includes a thin patterned layer including a two-dimensional array of poles forming one or more quadrupoles. The patterned layer design permits the use of very short poles and with a very dense spacing of the poles, so that the ion filter may be made very small. Also provided is a method for making the ion filter and the quadrupole mass spectrometer. The method involves forming the patterned layer of the ion filter in such a way that as the poles of the patterned layer are formed, they have the relative positioning and aligrnent for use in a final quadrupole mass spectrometer device.