Abstract: A semiconductor device includes: a semiconductor substrate having an active device region that includes a plurality of device cells and a termination region between the active device region and an edge of the semiconductor substrate; a field termination structure in the termination region and including a continuous region of a first conductivity type and a plurality of rings of the first conductivity type in the continuous region and having a higher average doping concentration than the continuous region; and a charge balance structure in the active device region and including interleaved columns of the first conductivity type and of a second conductivity type opposite the first conductivity type. The charge balance structure extends into the termination region below the field termination structure such that at least an outermost one of the columns of the first conductivity type is connected to the continuous region of the field termination structure.

Abstract: A silicon carbide device includes: a planar gate structure on a first surface of a silicon carbide substrate, the planar gate structure having a gate length along a lateral first direction; a source region of a first conductivity type extending under the planar gate structure over at least part of the gate length; a body region of a second conductivity type, the body region including a channel zone that adjoins the source region under the planar gate structure; and a shielding region of the second conductivity type covering the channel zone over at least 20% but less than 100% of the gate length, wherein a maximum dopant concentration in the shielding region is higher than a maximum dopant concentration in the body region.

Abstract: A semiconductor transistor device includes: a gate trench in a SiC semiconductor body; a channel region at a first side wall of the trench; and a diode region at a second side wall of the trench, the side walls lying opposite to each other in a transverse direction. As seen in a vertical cross-section perpendicular to the side walls, a first surface normal n1, perpendicular to the first side wall and pointing towards the channel region, is rotated between 174° to 178° in relation to a 4H-SiC Crystal a-direction, and a second surface normal n2, perpendicular to the second side wall and pointing towards the diode region, is rotated between ?2° to ?6° in relation to the 4H-SiC Crystal a-direction, or n1 is rotated between 178° to 182° in relation to a 4H-SiC Crystal m-direction and n2 is rotated between ?2° to 2° in relation to the 4H-SiC Crystal m-direction.

Abstract: A semiconductor device includes a SiC semiconductor body having a mesa between trench gate structures, with a one-sided channel region adjoining a first mesa sidewall of opposite first and second mesa sidewalls. A first conductivity type region adjoins the first mesa sidewall and a top surface of the mesa. A second conductivity type region adjoins the second mesa sidewall and the top surface, with a pn junction separating the first and second regions at the top surface. A width of the first region at the top surface alternates, along a longitudinal direction of the mesa, between first and second width ranges. The first width range is larger than 10% and smaller than 50% of the mesa width at the top surface. The second width range is larger than or equal to 50% and smaller than 90% of the mesa width at the top surface.

Abstract: The present application relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body comprising a first doping type region; a metallization on a first side of the SiC semiconductor body; an inorganic passivation layer system; a lateral edge of the inorganic passivation layer system arranged on the SiC semiconductor body, wherein the lateral edge of the inorganic passivation layer system is laterally offset inwards from a lateral edge of the SiC semiconductor body, the SiC semiconductor body being uncovered by the inorganic passivation layer system in an edge area, wherein a second doping type well is formed at the first side of the SiC semiconductor body in the first doping type region, the second doping type well extending from below the inorganic passivation layer system into the edge area.

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure is confined along a lateral second direction by a first gate sidewall of the gate structure and a second gate sidewall of the gate structure. The trench gate structure includes a first portion and a second portion laterally displaced from each other along the lateral first direction. In the first portion, the first gate sidewall extends to a first depth and, in the second portion, the first gate sidewall extends to a second depth along the vertical direction into the silicon carbide body. The second depth is greater than the first depth.

Abstract: A method of forming a wide band gap semiconductor device is proposed. The method includes forming a trench extending into a wide band gap semiconductor body from a first surface of the wide band gap semiconductor body. The method further includes forming a shielding region including introducing dopants of a first conductivity type into the wide band gap semiconductor body through at least one of a bottom side or a sidewall of the trench by ion implantation. Thereafter, the method further includes expanding the trench including an expansion process of forming a sacrificial oxide lining sidewalls and a bottom side of the trench by thermal oxidation and removing the sacrificial oxide.

Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

Abstract: A vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having opposite first and second surfaces. The SiC semiconductor body includes a transistor cell area including gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a sensor electrode and a first interlayer dielectric having a first interface to the sensor electrode and a second interface to at least one of the gate electrode or the gate interconnection. A conduction band offset at the first interface ranges from 1 eV to 2.5 eV. The vertical power semiconductor device further includes a second interface to at least one of the gate electrode or the gate interconnection. The second interlayer dielectric laterally adjoins to the first interlayer dielectric.

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

Abstract: A transistor device is disclosed. The transistor device includes a semiconductor body and plurality of transistor cells. Each transistor cell includes: a drift region and a source region of a first doping type; a body region of a second doping type complementary to the first doping type; a field shaping region of the second doping type connected to a source node; and a gate electrode connected to a gate node. The gate electrode is arranged in a trench extending from a first surface into the semiconductor body. The gate electrode is dielectrically insulated from the body region by a gate dielectric. At least portions of the gate electrode are dielectrically insulated from the drift region by a field dielectric. The field shaping region adjoins the trench. The field dielectric comprises a high-k dielectric.

Abstract: A power semiconductor device is proposed. The power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising transistor cells. Each of the transistor cells includes a gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes a first gate dielectric layer adjoining to the SiC semiconductor body. The gate dielectric structure further includes a second gate dielectric layer. The gate dielectric structure further includes charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Abstract: A semiconductor device includes a transistor having a plurality of gate trenches formed in a semiconductor substrate, the gate trenches patterning the semiconductor substrate into ridges. The transistor further includes a gate electrode arranged in at least one of the gate trenches. A source region, a channel region and a part of a current spread region are arranged in the ridges. The semiconductor device further includes a superjunction structure arranged at a larger distance to the source region than the channel region. The superjunction structure includes a first compensation region of the first conductivity type and a second compensation region of the second conductivity type. A doping concentration of the doped portion of the second conductivity type of the channel region decreases in a second horizontal direction intersecting the first horizontal direction from a region close to the gate electrode to a central portion of the ridge.

Abstract: A wide band gap semiconductor device is proposed. The wide band gap semiconductor device includes a wide band gap semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. A gate electrode structure is arranged in an active transistor area. The gate electrode structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the wide band gap semiconductor body. A gate interconnection structure is arranged outside of the active transistor area. The gate interconnection structure includes an interconnection electrode and an interconnection dielectric arranged between the interconnection electrode and the wide band gap semiconductor body. Dielectric constants of a main dielectric component of at least two of i) a part of the gate interconnection dielectric, or ii) a first part of the gate dielectric, or iii) a second part of the gate dielectric differ from one another.

Abstract: A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

Abstract: A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.

Abstract: A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

Abstract: A semiconductor device includes: a semiconductor substrate having an active device region that includes a plurality of device cells and a termination region between the active device region and an edge of the semiconductor substrate; a field termination structure in the termination region and including a continuous region of a first conductivity type and a plurality of rings of the first conductivity type in the continuous region and having a higher average doping concentration than the continuous region; and a charge balance structure in the active device region and including interleaved columns of the first conductivity type and of a second conductivity type opposite the first conductivity type. The charge balance structure extends into the termination region below the field termination structure such that at least an outermost one of the columns of the first conductivity type is connected to the continuous region of the field termination structure.