Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ?? LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: A circuit is configured to receive an input signal and to produce an output signal measuring a power of the input signal. The circuit includes a multiplier cell configured to multiply first and second signals, where each of the first and second signals includes a component related to the input signal and a component related to the output signal. The circuit also includes a controlled amplifier configured to amplify an intermediate signal produced by the multiplier cell, where an amplification provided by the controlled amplifier is a function of the output signal. The circuit could further include at least one first converting amplifier configured to generate the component related to the input signal and at least one second converting amplifier configured to generate the component related to the output signal. Transconductances of the converting amplifiers could be selected to configure the circuit as a linear or logarithmic RMS power detector.

Abstract: Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ?? LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals.

Abstract: Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals.

Abstract: A sigma-delta difference-of-squares RMS-to-DC converter and method for performing such a conversion in which an analog feedback signal is combined with an analog input signal, following which the combined signals are multiplied to produce an analog product signal that includes at least one signal component corresponding to a difference between a square of the analog feedback signal and a square of the analog input signal. This analog product signal is filtered and digitized to produce a digital output signal to be available for use downstream in or with the host system, with such digital output signal also being converted to the analog feedback signal.

Abstract: A sigma-delta difference-of-squares RMS-to-DC converter and method for performing such a conversion in which a square of an analog feedback signal is combined differentially with a square of an analog input signal, thereby producing an analog product signal that includes at least one signal component corresponding to a difference between such signal squares. This analog product signal is filtered and digitized to produce a digital output signal to be available for use downstream in or with the host system, with such digital output signal also being converted to the analog feedback signal.

Abstract: Described herein is technology for, among other things, reducing offset errors in RMS-to-DC converters. The technology involves generating first and second feedback signals with first and second feedback paths respectively. A multiplier is then employed to receive first and second signals and provide a third signal based on multiplying the first signal and the second signal. The first signal is based on an input signal and the first feedback signal, and the second signal is based on the input signal and the second feedback signal. A chopper is then employed to receive an output signal, which is based on the third signal, and a chopping signal, and in turn provide a fourth signal based on multiplying the output signal with the chopping signal. As a consequence, the fourth signal represents the output signal shifted to a frequency different than that of low-frequency noise components of the first and second signals.

Abstract: One embodiment of the present invention is directed to an apparatus for reducing errors affecting the intercept of a logarithmic device, the apparatus including a first switching device coupled to an input of the logarithmic device. The first switching device for switches the input of the logarithmic device between an input signal and a reference signal. The apparatus further includes a polarity switching device coupled to an output of the logarithmic device. The polarity switching device is configured to switch the polarity of an output signal of the logarithmic device when the logarithmic device is receiving one of the input signal and the reference signal. The apparatus further includes a low pass filter coupled to the polarity switching device.

Abstract: Quadrature demodulator and quadrature modulator which comprise a first oscillator and a second oscillator, a separate excitation signal being fed to the first and second oscillator to determine the time at which switching between two stable states takes place, and the quadrature demodulator and quadrature modulator further comprise excitation elements In the quadrature demodulator, an input signal is fed, which influences a parameter of one of the elements of the first and the second oscillator and produces a set of quadrature output signals. In the quadrature modulator, a first and second quadrature signals are fed to the quadrature modulator, which influences a parameter of one of the elements of the first and the second oscillator, and the quadrature modulator further comprises summing elements to produce a modulated output signal.

Abstract: Quadrature demodulator (10) and quadrature modulator (30) which comprise a first oscillator (11) and a second oscillator (12), a separate excitation signal being fed to the first osciallator (11) and second oscillator (12) in order to determine the point in time at which switching between two stable states lakes place, and the quadrature demodulator (10) and quadrature modulator (30) further comprise excitation means (17, 18). In the quadrature demodulator (10), an input signal Si(t) is fed, by means of which signal a parameter of one of the elements of the first and the second oscillator (11, 12) is influenced and a set of quadrature Output signals Io, Qn is produced.