Abstract: An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools.

Abstract: The invention teaches a system and method for temporarily buffering data written to a storage system by a host computer. The storage system includes direct access storage devices and a cache. The cache is used as the buffer for both caching and noncaching data records before destaging to a direct access storage device. Upon receipt of a channel program from a host computer containing data for records to be updated, the storage controller determines if the records are currently cached. If the records are not cached, a write miss has occurred. Upon a write miss the storage controller checks an attribute transmitted in the channel program to determine if the records have a regular format. Records having a known, regular format are buffered in cache until destaged by a background process.

Abstract: A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line.