Abstract: Thin film, multi-layered components wherein the layers are hermetically sealed with a re-flowed conductive sealant (e.g. Pb/Sn solder). The sealant is applied to an endless ground conductor at the peripheral edge of at least one of each pair of opposed substrate layers prior to registering the conductors and re-flowing the sealant. The microstrip conductors comprise thin film adhesion and seed layers and a covering metalization. The signal and ground conductors are terminated with solder balls and the signal and ground conductors are connected with micro vias that extend through the substrates.

Abstract: Thin film, multi-layered components wherein the layers are hermetically sealed with a re-flowed conductive sealant (e.g. Pb/Sn solder). The sealant is applied to an endless ground conductor at the peripheral edge of at least one of each pair of opposed substrate layers prior to registering the conductors and re-flowing the sealant. The microstrip conductors comprise thin film adhesion and seed layers and a covering metalization. The signal and ground conductors are terminated with solder balls and the signal and ground conductors are connected with micro vias that extend through the substrates.

Abstract: A thin film differential delay line configured in a strip line assembly on ceramic substrates for PECL logic applications. A number of alternative layered constructions are disclosed. Each assembly provides complementary serpentine conductors constructed in symmetrical arrangements, i.e. side-by-side, over-under and mirrored. Bordering ground conductors at the signal layer and adjacent ground planes layers shield the delay line conductors. Termination pads having plated through vias facilitate electrical couplings between the layers.