Abstract: A wedge locking element (10) for a locking device of a quick coupler A for coupling the pin P2 of an attachment to earth working machinery. The wedge locking element (10) has a sloping wedge surface (13). Projecting from the wedge surface (13) is an engagement surface (12) with which the attachment pin P2 can engage but not apply any substantial driving force to the wedge locking element (10) in the event of failure of a force maintaining the wedge locking element (10) in a position where the pin P2 is retained with the coupler A. The pin engagement surface (12) lies in a plane that is substantially in line with the direction in which the locking element (10) is, in use, moved by the driving force.

Abstract: A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Abstract: By locating the depth buffer of a 3D graphics rasterization pipeline in a dedicated high speed memory, bandwidth on a main bus can be eliminated that would otherwise result from hidden surface removal (HSR) hardware contained in the pipeline. Also, by reordering of read and write access commands to the depth buffer memory, it is possible to improve memory access throughput otherwise impacted by an increased latency of a read access.

Abstract: A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of microelectromechanical system (MEMS) display elements and a plurality of passive impedance network circuits coupled to said array and configured to provide row output voltages to drive said array. Each passive impedance network comprises an output to a row of display elements and three or more inputs. No more than one input is shared by two passive impedance networks.

Abstract: This patent discloses a system and method to compile a set of display points that define a two dimensional representation of a straight line graphic object using three dimensional rasterization algorithms. In one embodiment, a three dimensional (3D) graphics accelerator may receive data. The data may define three vertices (x0, y0, K0), (x1, y1, K1), and (x2, y2, K2) of a triangle primitive. Attributes K2=(K0+K1)/2 and coordinates (x0, y0), (x1, y1), and (x2, y2) form an isosceles triangle primitive. Coordinates (x0, y0) and (x1, y1) define a base of the isosceles triangle primitive. The isosceles triangle primitive may be rendered using the three dimensional rasterization algorithms to obtain the set of display points that define a two dimensional representation of the base of the isosceles triangle primitive.

Abstract: A three-dimensional (3D) graphics pipeline renders a sequence of images of 3D scenes each composed of a plural set of objects. The pipeline comprises an antialiasing oversampling mechanism to perform for a given image, at an early stage of the pipeline, oversampling on a portion of the objects of the given image.