Patents by Inventor Michael I. CURRENT
Michael I. CURRENT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901351Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.Type: GrantFiled: August 8, 2022Date of Patent: February 13, 2024Assignee: Silicon Genesis CorporationInventors: Michael I. Current, Theodore E. Fong
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Publication number: 20230299060Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.Type: ApplicationFiled: April 10, 2023Publication date: September 21, 2023Inventors: Theodore E. FONG, Michael I. CURRENT
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Publication number: 20230215857Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.Type: ApplicationFiled: August 8, 2022Publication date: July 6, 2023Inventors: Michael I. CURRENT, Theodore E. FONG
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Patent number: 11626392Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.Type: GrantFiled: February 12, 2021Date of Patent: April 11, 2023Assignee: Silicon Genesis CorporationInventors: Theodore E. Fong, Michael I. Current
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Patent number: 11410984Abstract: Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.Type: GrantFiled: October 8, 2021Date of Patent: August 9, 2022Assignee: Silicon Genesis CorporationInventors: Michael I. Current, Theodore E. Fong
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Publication number: 20210242184Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.Type: ApplicationFiled: February 12, 2021Publication date: August 5, 2021Inventors: Theodore E. FONG, Michael I. CURRENT
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Patent number: 10923359Abstract: Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.Type: GrantFiled: July 15, 2020Date of Patent: February 16, 2021Inventors: Thomas E Seidel, Michael I Current
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Patent number: 10923459Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.Type: GrantFiled: February 21, 2020Date of Patent: February 16, 2021Assignee: Silicon Genesis CorporationInventors: Theodore E. Fong, Michael I. Current
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Publication number: 20210020452Abstract: Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Inventors: Thomas E Seidel, Michael I Current
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Patent number: 10804252Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.Type: GrantFiled: February 14, 2020Date of Patent: October 13, 2020Assignee: Silicon Genesis CorporationInventors: Theodore E. Fong, Michael I. Current
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Publication number: 20200194409Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.Type: ApplicationFiled: February 21, 2020Publication date: June 18, 2020Inventors: Theodore E. FONG, Michael I. CURRENT
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Publication number: 20200185364Abstract: A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Theodore E. FONG, Michael I. CURRENT
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Patent number: 10573627Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.Type: GrantFiled: August 7, 2018Date of Patent: February 25, 2020Assignee: Silicon Genesis CorporationInventors: Theodore E. Fong, Michael I. Current
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Publication number: 20180350785Abstract: Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.Type: ApplicationFiled: August 7, 2018Publication date: December 6, 2018Inventors: Theodore E. FONG, Michael I. CURRENT
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Patent number: 10049915Abstract: A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.Type: GrantFiled: December 1, 2017Date of Patent: August 14, 2018Assignee: SILICON GENESIS CORPORATIONInventors: Theodore E. Fong, Michael I. Current
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Publication number: 20180175008Abstract: A device is formed by providing a first substrate, depositing a thickness of range compensating material on a first surface of the first substrate, implanting ions into the first substrate, the ions traveling through the range compensating material to define a cleave profile in the first substrate, the cleave profile including a contour that corresponds to the thickness of absorber material, removing the absorber material, and cleaving the first substrate at the cleave profile, thereby exposing the contour. A substrate with high thermal conductivity in which the contour defines a coolant channel effectively removes heat from a three-dimensional integrated circuit.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Theodore E. FONG, Michael I. CURRENT
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Publication number: 20180082989Abstract: A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.Type: ApplicationFiled: December 1, 2017Publication date: March 22, 2018Inventors: Theodore E. Fong, Michael I. Current
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Publication number: 20170301657Abstract: A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.Type: ApplicationFiled: June 8, 2017Publication date: October 19, 2017Inventors: Theodore E. FONG, Michael I. CURRENT
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Patent number: 9704835Abstract: A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.Type: GrantFiled: January 11, 2016Date of Patent: July 11, 2017Assignee: SILICON GENESIS CORPORATIONInventors: Theodore E. Fong, Michael I. Current
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Publication number: 20160379828Abstract: A conformal thermal ALD film having a combination of elements containing a dopant, such as boron (or phosphorus), and an oxide (or nitride), in intimate contact with a semiconductor substrate said combination having stable ambient and thermal annealing properties providing a shallow (less than ˜100 A) diffused (or recoil implanted) dopant, such as boron (or phosphorus) profile, into the underlying semiconductor substrate.Type: ApplicationFiled: June 23, 2016Publication date: December 29, 2016Inventors: Anil U. Mane, Thomas E. Seidel, Michael I. Current, Alexander Goldberg, Jeffrey W. Elam