Abstract: A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.

Abstract: A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.

Abstract: System and techniques for variable epoch spike train filtering are described herein. A spike trace storage may be initiated for an epoch. Here, the spike trace storage is included in a neural unit of neuromorphic hardware. Multiple spikes may be received at the neural unit during the epoch. The spike trace storage may be incremented for each of the multiple spikes to produce a count of received spikes. An epoch learning event may be obtained and a spike trace may be produced in response to the epoch learning event using the count of received spikes in the spike trace storage. Network parameters of the neural unit may be modified using the spike trace.

Abstract: An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendrite ID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment.

Abstract: An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.

Abstract: Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.

Abstract: System and techniques for variable epoch spike train filtering are described herein. A spike trace storage may be initiated for an epoch. Here, the spike trace storage is included in a neural unit of neuromorphic hardware. Multiple spikes may be received at the neural unit during the epoch. The spike trace storage may be incremented for each of the multiple spikes to produce a count of received spikes. An epoch learning event may be obtained and a spike trace may be produced in response to the epoch learning event using the count of received spikes in the spike trace storage. Network parameters of the neural unit may be modified using the spike trace.

Abstract: An electronic neural core circuit is provided, comprising a processor, and a memory. The memory comprises a plurality of neural compartments, each compartment comprising a first state variable representing a first state of the neural compartment, and a second state variable representing a second state of the neural compartment. The processor is configured to, for a first neural compartment: receive a synaptic input, perform first and second state variable operations, join operations utilizing input from state variables from another compartment that has been previously processed, thereby producing a join operation results, and produce a state variable output.

Abstract: A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.

Abstract: Aspects of the embodiments are directed to computationally modeling a filtered temporal spike train trace in the digital domain. A current value of the trace, and a parameter defining temporal behavior of the trace, are each stored. A decay function of the trace is computed based on the parameter and on passage of discrete time increments. Stimulus signaling is received, and an input response function of the trace is computed based on the stimulus signaling. A stochastic computation of the trace decay function may be performed based on a generated randomization value. In some embodiments, a delayed computation of the trace decay function may be performed.

Abstract: An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.

Abstract: Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.

Abstract: An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendriteID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment.

Abstract: An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.

Abstract: An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.

Abstract: An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.

Abstract: An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.

Abstract: The specification describes a method of storing alphanumeric characters in a graphics display terminal comprising a raster-scan display device and a refresh buffer including a plurality of bit planes each having a respective bit storage location corresponding to each addressable pel position on the screen of the display device. In the method, a first bit plane stores high resolution luminance data defining alphanumeric characters each as a selection of "on" bits within a respective n.times.m array where n is the width of the character box in the scan line direction, and at least one further bit plane stores low resolution color data for the characters. The attribute plane comprises a respective n-bit set of storage locations which corresponds to each n-bit wide by one pel deep portion of a character box in the luminance plane and defines at least the color and/or intensity of the foreground and background of the character for the width of the character box in respect of a single scan line.

Abstract: An electronic assembly with forced convection cooling comprises an elongate support plate having a plurality of electronic equipment cabinets mounted side by side on a common surface of the plate in the longitudinal direction thereof. At least one air distribution channel extends longitudinally of the plate in the said common surface, and a cooling fan is mounted on the same surface of the plate as the cabinets for forcing air along the air distribution channel and into the cabinets for cooling electrical components therein.The assembly preferably includes means for directing air from the channel selectively in different quantities to different components according to their cooling requirements, such means including a plurality of secondary air distribution channels which branch laterally from the first mentioned channel, and means for confining air from the first mentioned channel to flow into the secondary channels.

Abstract: A processor intercommunication system includes a plurality of stations which are interconnected by a transmission link, each station having an associated processor. Further, each station comprises means which provide a data link protocol mechanism for establishing and maintaining a multiplicity of logical connections or transfer sessions between the station and several other stations. Thus application programs of all kinds in the processors can communicate with programs or data files in remote processors and need not be involved in communication operations which are handled by the stations. Link access circuitry is provided also in each station for absorbing the physical and topological characteristics of the transmission link so that the data protocol circuitry establishing and maintaining logical connections is independent of these characteristics.