Abstract: A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.

Abstract: An improved method is provided for seamlessly combining adjacent subchannels in a signal processing system. Each adjacent subchannel is defined to include a first and a second linear phase digital filter, where the filters are implemented using digital circuitry having a plurality of registers. Prior to summing the two adjacent channels, a delay is introduced into one of the two filters in each of the subchannels, such that the delay is equal to the delay associated with one register in the digital circuitry. The two adjacent subchannels are then combined to form a composite channel that exhibits linear phase.

Abstract: A design tool and method for characterizing a circuit at a hardware level includes the steps of generating a behavioral level description of the circuit and generating a netlist from the behavioral level description. Reference equations are generated from the netlist and are translated into numeric and symbolic C-code. The symbolic C-code is compared to the numeric C-code for validation. The reference equations are translated into numeric and symbolic HDL-code. The symbolic HDL-code is compared to the numeric HDL-code for validation. The symbolic C-code is compiled and simulated. A C-code equation file is generated. The symbolic HDL-code is compiled and simulated. A HDL-code equation file is generated. A symbolic manipulation program is used to solve for a difference between the C-code equation file and the HDL-code equation file. If there are no unexpected differences, equivalence is established.

Abstract: A method and computer system formally verifies a synthesis of integrated circuit designs that include pipeline registers. A hardware description language (HDL) representation of an integrated circuit is parsed. Components and connections of the HDL representation are identified. Pipeline register components of the HDL representation are removed. The removed pipeline register components are replaced with a conductor. Pipeline register components are added between output logic gates and output registers of the HDL representation to create a new HDL representation. Formal verification of the new HDL representation is performed using a verification tool.

Abstract: A design tool and method for characterizing a circuit at a hardware level includes the steps of generating a behavioral level description of the circuit and generating a netlist from the behavioral level description. Reference equations are generated from the netlist and are translated into numeric and symbolic C-code. The symbolic C-code is compared to the numeric C-code for validation. The reference equations are translated into numeric and symbolic HDL-code. The symbolic HDL-code is compared to the numeric HDL-code for validation. The symbolic C-code is compiled and simulated. A C-code equation file is generated. The symbolic HDL-code is compiled and simulated. A HDL-code equation file is generated. A symbolic manipulation program is used to solve for a difference between the C-code equation file and the HDL-code equation file. If there are no unexpected differences, equivalence is established.

Abstract: A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.

Abstract: An improved method is provided for seamlessly combining adjacent subchannels in a signal processing system. Each adjacent subchannel is defined to include a first and a second linear phase digital filter, where the filters are implemented using digital circuitry having a plurality of registers. Prior to summing the two adjacent channels, a delay is introduced into one of the two filters in each of the subchannels, such that the delay is equal to the delay associated with one register in the digital circuitry. The two adjacent subchannels are then combined to form a composite channel that exhibits linear phase.

Abstract: A computer-implemented design tool architecture provides a mechanism for characterizing a circuit at a hardware level. The tool architecture has a medium for storing a description of an application specific integrated circuit (ASIC), where the description describes the ASIC at a behavioral level of a hierarchy. A library of foundry primitives map known ASIC components to code sets for a hardware description language (HDL). The tool architecture further includes a command interpreter for generating an electronic file based on a set of predefined computer-based commands such that the electronic file characterizes the circuit at the hardware level. The hardware level is at a lower level in the hierarchy than the behavioral level.

Abstract: A unique transistor model and methods for analyzing the model are disclosed. The transistor model of the present invention is simple and requires specification of a minimal number of parameters to simulate transistor operation. Three analysis methods are disclosed, each having unique circumstances for application A first method is premised on sampling all waveforms in the circuit and determining the operating point of the transistor. The first method assumes an input of an arbitrary periodic waveform. The first method is very flexible and may be used with a wide range of models other than the disclosed model. A second and a third method are premised on input and output waveform clipping. The second method assumes a single tone input into the transistor. The third method is a combination of features from the first and second methods. The third method is computationally efficient and assumes an arbitrary periodic input waveform.

Abstract: A system and method for determining dispersion of intermodulation power in a satellite communication system or any other system which can be mathematically modeled as a matrix multiplication followed by an instantaneous nonlinearity and another matrix multiplication include determining a matrix (V) representing amplitudes and frequencies of signals generated by a digital processor and input to a plurality of amplifiers. A matrix (M) representing signal propagation from the amplifiers to a destination is used to determine the intermodulation power at the destination within each transmitted beam at each intermodulation distortion frequency. The intermodulation distortion frequencies are determined based on sums and differences of component frequencies corresponding to the user signals.

Abstract: An algorithm (20) or method (20) for verifying that a system hierarchically built from smaller components implements a desired equation that represents the system. Symbolic data is clocked (24) through the system by processing a symbolic test vector using linked equations (22) written (21) for each component of the system. A resulting symbolic equation generated at the output of the system is recorded (25). The symbolic equation is then compared (26) with the desired equation for the system using a symbolic manipulation tool. If the comparison generates a zero difference, the system correctly implements the desired equation representative of the system, and vice-versa.

Abstract: An automatic and iterative simulation method for adjusting linearizer parameters to achieve desired AM/AM and AM/PM characteristics is disclosed. The disclosed method includes the steps of choosing a set of linearizer parameters, modeling the performance of the linearizer circuit and the power amplifier to calculate a performance index. The performance index is compared to a threshold. The method continues to iterate until the performance index is acceptable in comparison to the threshold. When the process is completed, the linearizer parameters are output for use by the designer. The disclosed method eliminates the need to engage in trial and error methods in a laboratory when combining a linearizer and a power amplifier to produce linear output characteristics.

Abstract: Apparatus and methods that compensate for the effects of gain and phase variations of a high power amplifier in the presence of multicarrier traffic. The calibration system and method impose negligible degradation to the multicarrier traffic processed by the high power amplifier. A calibration signal generator is used to generate a plurality of nondisrupting calibration signals, such as pseudorandom numbers, which are also summed and combined with the multicarrier traffic signals. The plurality of nondisrupting calibration signals are also combined to produce a combined nondisrupting calibration signal. Each of the nondisrupting calibration signals is selectively output and is combined with sampled versions of the amplified multicarrier traffic signals produced by the high power amplifier to despread them.

Abstract: An anti-jackknifing and skidding control system for trailer trucks is described, wherein a linear accelerometer located on the rear of the trailer detects left or right skidding and provides automatic differential braking action to the left or right wheels depending on the direction of skidding to be corrected. The system distinguishes a usual coordinated turn or truck maneuver from a skidding condition to correct only for the latter. In addition, wheel locking is prevented by releasing the braking action, when such wheel locking is detected.