Abstract: A single patch on an integrated circuit is arranged to patch any one of four different logical states into the circuit, according to whether the pin is grounded, floating, coupled to a supply rail via a resistor, or coupled to the supply rail directly. In one embodiment, the voltage thresholds of three transistors are arranged so that they switch on successively in response to successively higher voltages on the patch pin, thereby controlling the binary logic signals at each of two output points in the circuit; in the other embodiment, multi-emitter transistors are arranged with differing current thresholds to achieve the same result.

Abstract: An interface circuit for use in a data transmission system has a first port for connection to a 16 wire data highway of the type proposed by the I.E.C. (International Electrochemical Commission) for the interconnection of instruments, and a second port capable of being connected to an eight-wire or two-wire data link. The interface circuit includes an encoding circuit operative to encode at least some commands applied to the first port, and an enabling circuit for selectively enabling data applied to the data terminals of the first port and the encoded commands to pass to the second port.