Patents by Inventor Michael I. Thompson
Michael I. Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7924859Abstract: A method and system for transferring iSCSI protocol data units (“PDUs”) to a host system is provided. The system includes a host bus adapter with a TCP/IP offload engine. The HBA includes, a direct memory access engine operationally coupled to a pool of small buffers and a pool of large buffers, wherein an incoming PDU size is compared to the size of a small buffer and if the PDU fits in the small buffer, then the PDU is placed in the small buffer. If the incoming PDU size is compared to a large buffer size and if the incoming PDU size is less than the large buffer size then the incoming PDU is placed in the large buffer. If the coming PDU size is greater than a large buffer, then the incoming PDU is placed is more than one large buffer and a pointer to a list of large buffers storing the incoming PDU is placed in a small buffer.Type: GrantFiled: March 19, 2009Date of Patent: April 12, 2011Assignee: QLOGIC, CorporationInventors: Derek Rohde, Michael I. Thompson
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Patent number: 7830919Abstract: A method for processing IP datagrams using an outbound processing state machine, in an outbound processor, wherein the IP datagrams are generated by a host system is provided. The method includes, creating an IOCB with plural host memory addresses that define host data to be sent and a host memory address of a network control block (“NCB”) used to build network protocol headers, wherein the host sends the IOCB to the outbound processor. The outbound processor reads the NCB from host memory and creates an IP and MAC level protocol header(s) for a data packet(s) used to send the IP data. If a datagram fits into an IP packet, the outbound processor builds headers to send the datagram and then uses the plural host memory addresses defining the host data to read the data from the host, places the data into the packet and sends the packet.Type: GrantFiled: February 19, 2009Date of Patent: November 9, 2010Assignee: QLOGIC, CorporationInventor: Michael I. Thompson
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Patent number: 7761608Abstract: A system with a host bus adapter (“HBA”) having a TCP/IP offload engine is provided. The HBA includes logic for concurrently processing markers, data integrity fields (“DIFs”) and digests by using plural counters that count words in a data stream and individual routing bits are set for markers, DIFs and digests based on the plural counter values. When a counter reaches a certain threshold value, then locator bits are set for a field and the locator bits are forwarded with the data stream. A marker counter is incremented when each word in a data stream passes by the marker counter and markers can be inserted at a programmed interval. For DIF calculation an offset of a first byte in a DMA transfer and partial cyclic redundancy code value is seeded into a DIF location counter, which is incremented for each byte of data that passes by the DIF location counter.Type: GrantFiled: September 1, 2004Date of Patent: July 20, 2010Assignee: QLOGIC, CorporationInventors: Derek Rohde, Bruce A. Klemin, Michael I. Thompson
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Patent number: 7639715Abstract: Method and system for receiving and sending network packets from a network is provided. The system includes, a host processor that executes an operating system for a host system and at least one application that runs in a context that is different from a context of the operating system; and a network adapter with a hardware device that can run a network protocol stack, wherein the application can access the network adapter directly via an application specific interface layer without using the operating system.Type: GrantFiled: September 9, 2005Date of Patent: December 29, 2009Assignee: QLOGIC, CorporationInventors: Douglas E. O'Neil, Michael I. Thompson
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Publication number: 20090304016Abstract: A method and system for transferring iSCSI protocol data units (“PDUs”) to a host system is provided. The system includes a host bus adapter with a TCP/IP offload engine. The HBA includes, a direct memory access engine operationally coupled to a pool of small buffers and a pool of large buffers, wherein an incoming PDU size is compared to the size of a small buffer and if the PDU fits in the small buffer, then the PDU is placed in the small buffer. If the incoming PDU size is compared to a large buffer size and if the incoming PDU size is less than the large buffer size then the incoming PDU is placed in the large buffer. If the coming PDU size is greater than a large buffer, then the incoming PDU is placed is more than one large buffer and a pointer to a list of large buffers storing the incoming PDU is placed in a small buffer.Type: ApplicationFiled: March 19, 2009Publication date: December 10, 2009Inventors: Derek Rohde, Michael I, Thompson
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Patent number: 7522623Abstract: A method and system for transferring iSCSI protocol data units (“PDUs”) to a host system is provided. The HBA includes, a direct memory access engine operationally coupled to a pool of small buffers and a pool of large buffers, wherein an incoming PDU size is compared to the size of a small buffer and if the PDU fits in the small buffer, then the PDU is placed in the small buffer. The incoming PDU size is compared to a large buffer size and if the incoming PDU size is less than the large buffer size then the incoming PDU is placed in the large buffer. If the coming PDU size is greater than a large buffer, then the incoming PDU is placed is more than one large buffer and a pointer to a list of large buffers storing the incoming PDU is placed in a small buffer.Type: GrantFiled: September 1, 2004Date of Patent: April 21, 2009Assignee: QLOGIC, CorporationInventors: Derek Rohde, Michael I. Thompson
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Patent number: 7515612Abstract: A method for processing IP datagrams using an outbound processing state machine in an outbound processor, wherein the IP datagrams are generated by a host system is provided. The method includes, creating an IOCB with plural host memory addresses that define host data to be sent and a host memory address of a network control block (“NCB”) used to build network protocol headers, wherein the host sends the IOCB to the outbound processor. The outbound processor reads the NCB from host memory and creates an IP and MAC level protocol header(s) for a data packet(s) used to send the IP data. If a datagram fits into an IP packet, the outbound processor builds headers to send the datagram and then uses the plural host memory addresses defining the host data to read the data from the host, places the data into the packet and sends the packet.Type: GrantFiled: July 15, 2003Date of Patent: April 7, 2009Assignee: QLOGIC, CorporationInventor: Michael I. Thompson
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Patent number: 7496042Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fibre Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: GrantFiled: July 7, 2004Date of Patent: February 24, 2009Assignee: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Publication number: 20080282069Abstract: Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.Type: ApplicationFiled: May 9, 2008Publication date: November 13, 2008Inventors: Bruce A. Klemin, Michael I. Thompson
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Patent number: 7447874Abstract: Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.Type: GrantFiled: October 18, 2005Date of Patent: November 4, 2008Assignee: QLOGIC, CorporationInventors: Bruce A. Klemin, Michael I. Thompson
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Patent number: 7420991Abstract: A method for sending/receiving a TCP segment is provided. The sending process includes, determining if a TCP port can be offloaded; saving a host system's time stamp value; replacing a host system's time stamp value with a TCP offload engine (“TOE”) adapter's time stamp value; and sending the TCP segment via the TOE adapter. The receiving process includes verifying if a TCP port is being offloaded by a host system to the TOE adpter; retrieving the host system's time stamp value; and inserting the host system's time stamp value in the received TCP segment before the forwarding the received TCP segment to the host system.Type: GrantFiled: April 1, 2005Date of Patent: September 2, 2008Assignee: QLOGIC, CorporationInventors: Ying P. Lok, Ronald M. Mercer, David C. Somayajulu, Shashank Pandhare, Michael I. Thompson
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Patent number: 7403542Abstract: A system for transmitting and receiving TCP/IP data packets using a hardware engine is provided. The system includes an inbound MAC Receive state machine for processing MAC frames received from a network; an inbound IP verifier state machine for verifying IP packet headers; an inbound IP fragment processing state machine for processing and reassembling IP fragments; and an inbound TCP state machine for processing TCP segments received from an IP layer. The system also includes an outbound MAC Transmit state machine that sends MAC frames to a network; an outbound IP state machine that processes IP data to be passed to a MAC layer for transmission; and an outbound TCP state machine that processes TCP data to be passed to the IP layer for transmission.Type: GrantFiled: July 15, 2003Date of Patent: July 22, 2008Assignee: QLOGIC, CorporationInventor: Michael I. Thompson
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Patent number: 7024590Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fiber Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: GrantFiled: July 7, 2004Date of Patent: April 4, 2006Assignee: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Patent number: 6938189Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fiber Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: GrantFiled: July 7, 2004Date of Patent: August 30, 2005Assignee: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Patent number: 6888800Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fiber Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for, monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: GrantFiled: November 9, 1999Date of Patent: May 3, 2005Assignee: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Publication number: 20040264365Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fibre Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: ApplicationFiled: July 7, 2004Publication date: December 30, 2004Applicant: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Publication number: 20040257984Abstract: Methods and associated hub arrangements are described for use in diagnosis and recovery in high performance digital loops such as, for example, those seen in Fibre Channel systems. In one system having a hub configured for interconnection of a plurality of stations as part of a digital system such that digital data flows between the stations based on operational status of the system, an arrangement forms part of the hub which arrangement is connectable at points within the hub and between at least two different pairs of the stations for monitoring certain characteristics of the data in a way which provides for non-invasive identification of one or more conditions related to the operational status of the system.Type: ApplicationFiled: July 7, 2004Publication date: December 23, 2004Applicant: Emulex Design & Manufacturing CorporationInventors: Bruce E. Johnson, Thomas J. Hammond-Doel, Donna M. Jollay, Michael I. Thompson
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Patent number: 6425034Abstract: A FC controller that interfaces between a host system and a 10-bit FC interface is herein described. The FC controller acts as both a FCP initiator and FCP target device and has the capability to receive and process SCSI I/O requests received from a FC and a host system. The FC controller can process both multiple inbound and outbound sequences simultaneously since it does not employ a processor-based architecture. Rather, the FC controller relies on specialized circuitry that can operate in a relatively independent manner so that multiple tasks are performed concurrently thereby achieving a faster throughput and data transfer rate.Type: GrantFiled: October 30, 1998Date of Patent: July 23, 2002Assignee: Agilent Technologies, Inc.Inventors: Joseph H. Steinmetz, Matthew P. Wakeley, Bryan J. Cowger, Michael I. Thompson
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Patent number: 5522039Abstract: A method and apparatus are presented for an improved data transferring technique between a network and a computing system. A network adapter implements a data transfer from a network to the memory of a destination computing system, accumulating a checksum of all data transferred. The dedicated hardware allows data to be transferred through it and a checksum to be accumulated without intervention by the processor of the destination computing system. Software corrections can generate a checksum of the header data and then generate a net checksum by subtracting the header checksum from the gross checksum accumulated by the dedicated hardware, thus achieving the desired result with minimal intervention by the processor of the destination computing system.Type: GrantFiled: September 9, 1993Date of Patent: May 28, 1996Assignee: Hewlett-Packard CompanyInventors: Robert D. Snyder, Paul R. Zimmer, Michael I. Thompson, Paul T. Congdon, K. Monroe Bridges, III
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Patent number: 5491802Abstract: A computing system is connected to a network. The computing system includes a network adapter and a main memory. The network adapter receives from the network a network packet having a plurality of headers. The network adapter inserts at least one pad byte within one of the plurality of headers to cause the plurality of headers in the network packet to be aligned along predetermined multi-byte boundaries. For example, the multi-byte boundaries are four-byte boundaries. After inserting the at least one pad byte, the network adapter forwards the network packet to the main memory.Type: GrantFiled: May 29, 1992Date of Patent: February 13, 1996Assignee: Hewlett-Packard CompanyInventors: Michael I. Thompson, Paul T. Congdon, John L. Burnett, Frank Fiduccia, deceased