Abstract: The current document is directed to a family of integrated hardware controllers that provides for cost-effective, high-bandwidth, and scalable incorporation of SSDs into large, distributed-computer systems. Certain implementations of the integrated hardware controller include dual media-access controllers for connection to one or more local area networks, remote-direct-memory-access (“RDMA”) controllers for supporting RDMA protocols over the local area network, an NVMe controller that provides access to an SSD. In certain integrated-hardware-controller implementations, the RDMA and NVMe controllers are implemented in one of a field programmable gate array (“FPGA”) and application-specific integrated circuit (“ASIC”).

Abstract: With CRC-code-computation logic used in electronic-communications hardware, many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. A component-efficient CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

Abstract: The current document is directed to component-efficient CRC-code-computation logic used in electronic-communications hardware. Many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. The currently disclosed CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix.

Abstract: One implementation of an NVMe storage system uses NVMe over Fabric (NVMf) SSDs. This implementation is built using off-the-shelf RDMA Network Interface Cards (RNIC) to connect the server to the network and then to the NVMf SSDs. The current document discloses a split implementation with the PCI Express/NVMe interface on an NVMe Initiator board plugged into a server and the Flash implemented on one or many network attached Flash (NVMf) devices.