Abstract: A hardware implementations of Montgomery modular multiplication are described. The number of components as well as the number of cycles may be reduced by using a lookup table and multiplexer for selecting terms to be added during calculations. Also a loop unrolling technique may be used improve performance. A chain of pipeline adder modules and a chain of delay and shift modules may be used to pipeline calculations of multiple sets of operands.

Abstract: A hardware implementations of Montgomery modular multiplication are described. The number of components as well as the number of cycles may be reduced by using a lookup table and multiplexer for selecting terms to be added during calculations. Also a loop unrolling technique may be used improve performance. A chain of pipeline adder modules and a chain of delay and shift modules may be used to pipeline calculations of multiple sets of operands.

Abstract: A network gateway device has a physical interface for connection to a medium. The device has an ingress processor system for ingress processing of all or part of packets received from the physical interface and for sending ingress processed packets for egress processing. The device has an egress processor system for receiving ingress processed packets and for egress processing of all or part of received packets for sending to physical interface. Interconnections are provided, including an interconnection between the ingress processor and the egress processor, including an interconnection between the ingress processor and the physical interface, and including an interconnection between the ingress processor and the physical interface. A packet queue is provided with packets awaiting transmission. The packet queue may be the exclusive buffer for packets between packets entering the device and packet transmission. The packets may exit the device at a rate of the line established at the physical interface.

Abstract: A network gateway device is provided with a network physical interface for receiving and transmitting data and for receiving packets for transmission and forwarding packets from received data. A packet processor is provided that provides for a key exchange and hosts a security association (SA) used for encryption and decryption for communication with a network peer. The packet processor includes an ingress processing security subsystem with a decryption processor for decrypting packets and an egress processing security subsystem for encrypting packets. One or both of the ingress processing security subsystem and the egress processing security subsystem receiving one or both of ingress and egress SAs. The packet processor may include a processor subsystem for handling key exchanges and for distributing SAs to the ingress processing security subsystem and the egress processing security subsystem.