Patents by Inventor Michael J. Barbieri

Michael J. Barbieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
    Patent number: 9786633
    Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 10, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Peter G. Murphy, Karen E. Magoon, Noyan Kinayman, Michael J. Barbieri, Timothy M. Hancock, Mark A. Gouker
  • INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES
    Publication number: 20170098627
    Abstract: A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Application
    Filed: April 23, 2015
    Publication date: April 6, 2017
    Inventors: Rabindra N. Das, Peter G. Murphy, Karen E. Magoon, Noyan Kinayman, Michael J. Barbieri, Timothy M. Hancock, Mark A. Gouker